add mips1 and mips32r2 isa definitions

5 files changed, 650 insertions, 2 deletions

diff --git a/include/melf.h b/include/melf.h
index a1c88c2..cf0a1b5 100644
--- a/include/melf.h
+++ b/include/melf.h
@@ -6,6 +6,7 @@
 #include <elf.h>
 #include <arpa/inet.h>
 
+/// mips is a big endian system
 #if __BYTE_ORDER == __LITTLE_ENDIAN
 #define B32(n) (__bswap_constant_32(n))
 #define B16(n) (__bswap_constant_16(n))
@@ -32,7 +33,7 @@ static const Elf32_Ehdr MIPS_ELF_EHDR =
 	.e_machine = B16(EM_MIPS),
 	.e_version = B32(EV_CURRENT),
 	.e_entry = 0x00,
-	.e_flags = B32(EF_MIPS_ARCH_32R6 | EF_MIPS_NAN2008 | EF_MIPS_ABI_O32),
+	.e_flags = 0x00,
 	.e_ehsize = B16(sizeof(Elf32_Ehdr)),
 	.e_phentsize = B16(sizeof(Elf32_Phdr)),
 	.e_shentsize = B16(sizeof(Elf32_Shdr)),
diff --git a/include/mips32.h b/include/mips.h
index e2b86b7..8155eb7 100644
--- a/include/mips32.h
+++ b/include/mips.h
@@ -43,6 +43,42 @@ enum mips32_register {
 	MIPS32_REG_RA   = 31,
 };
 
+/* all mips fp registers $f0-$f31 */
+enum mips32_fp_register {
+	MIPS32_REG_F0  =  0,
+	MIPS32_REG_F1  =  1,
+	MIPS32_REG_F2  =  2,
+	MIPS32_REG_F3  =  3,
+	MIPS32_REG_F4  =  4,
+	MIPS32_REG_F5  =  5,
+	MIPS32_REG_F6  =  6,
+	MIPS32_REG_F7  =  7,
+	MIPS32_REG_F8  =  8,
+	MIPS32_REG_F9  =  9,
+	MIPS32_REG_F10 = 10,
+	MIPS32_REG_F11 = 11,
+	MIPS32_REG_F12 = 12,
+	MIPS32_REG_F13 = 13,
+	MIPS32_REG_F14 = 14,
+	MIPS32_REG_F15 = 15,
+	MIPS32_REG_F16 = 16,
+	MIPS32_REG_F17 = 17,
+	MIPS32_REG_F18 = 18,
+	MIPS32_REG_F19 = 19,
+	MIPS32_REG_F20 = 20,
+	MIPS32_REG_F21 = 21,
+	MIPS32_REG_F22 = 22,
+	MIPS32_REG_F23 = 23,
+	MIPS32_REG_F24 = 24,
+	MIPS32_REG_F25 = 25,
+	MIPS32_REG_F26 = 26,
+	MIPS32_REG_F27 = 27,
+	MIPS32_REG_F28 = 28,
+	MIPS32_REG_F29 = 29,
+	MIPS32_REG_F30 = 30,
+	MIPS32_REG_F31 = 31,
+};
+
 /* mips instruction */
 union mips32_instruction {
 	/* raw ins */
@@ -77,6 +113,48 @@ union mips32_instruction {
 		uint32_t bfunct :  5;
 		uint32_t        : 11;
 	};
+	/* coprocessor */
+	struct {
+		uint32_t        : 21;
+		uint32_t cfunct :  5;
+		uint32_t        :  6;
+	};
+	/* flags */
+	struct {
+		// 6 bit
+		uint32_t        :  5;
+		uint32_t sc     :  1; // interrupt
+		// 5 bit
+		uint32_t rv     :  1; // rotate variable
+		uint32_t        :  3;
+		uint32_t hb     :  1; // hazard barrier
+		// 5 bit
+		uint32_t        :  5;
+		// 5 bit
+		uint32_t tf     :  1; // true false
+		uint32_t nd     :  1; //
+		uint32_t cc     :  3; // code
+		// 5 bit
+		uint32_t r      :  1; // rotate
+		uint32_t        :  3;
+		uint32_t c0     :  1; // cop0
+		// 6 bit
+		uint32_t        :  6;
+	};
+	/* break code */
+	struct {
+		uint32_t        :  6;
+		uint32_t code   : 20;
+		uint32_t        :  6;
+	};
+	/* floating point */
+	struct {
+		uint32_t        :  6;
+		uint32_t fd     :  5;
+		uint32_t fs     :  5;
+		uint32_t ft     :  5;
+		uint32_t        : 11;
+	};
 } __attribute__((packed));
 
 /// grammer syntax:
diff --git a/include/mips1.h b/include/mips1.h
new file mode 100644
index 0000000..e7fd047
--- /dev/null
+++ b/include/mips1.h
@@ -0,0 +1,227 @@
+/* Copyright (c) 2024 Freya Murphy */
+
+#ifndef __MIPS1_H__
+#define __MIPS1_H__
+
+#include <mlimits.h>
+#include <stdint.h>
+#include <mips.h>
+
+// TODO:
+// CFC1
+// CTC1
+// COP0-3
+// LWC1-3
+// SWC1-3
+
+/* mips instructions */
+enum mips1_instruction_type {
+	MIPS1_INS_ADD,
+	MIPS1_INS_ADDI,
+	MIPS1_INS_ADDIU,
+	MIPS1_INS_ADDU,
+	MIPS1_INS_AND,
+	MIPS1_INS_ANDI,
+	MIPS1_INS_BC1F,
+	MIPS1_INS_BC1T,
+	MIPS1_INS_BEQ,
+	MIPS1_INS_BGEZ,
+	MIPS1_INS_BGEZAL,
+	MIPS1_INS_BGTZ,
+	MIPS1_INS_BLEZ,
+	MIPS1_INS_BLTZAL,
+	MIPS1_INS_BLTZ,
+	MIPS1_INS_BNE,
+	MIPS1_INS_BREAK,
+	MIPS1_INS_CLO,
+	MIPS1_INS_CLZ,
+	MIPS1_INS_DIV,
+	MIPS1_INS_DIVU,
+	MIPS1_INS_ERET,
+	MIPS1_INS_J,
+	MIPS1_INS_JAL,
+	MIPS1_INS_JALR,
+	MIPS1_INS_JR,
+	MIPS1_INS_LB,
+	MIPS1_INS_LBU,
+	MIPS1_INS_LH,
+	MIPS1_INS_LHU,
+	MIPS1_INS_LL,
+	MIPS1_INS_LUI,
+	MIPS1_INS_LW,
+	MIPS1_INS_LWC1,
+	MIPS1_INS_LWL,
+	MIPS1_INS_LWR,
+	MIPS1_INS_MADD,
+	MIPS1_INS_MADDU,
+	MIPS1_INS_MFC0,
+	MIPS1_INS_MFC1,
+	MIPS1_INS_MFHI,
+	MIPS1_INS_MFLO,
+	MIPS1_INS_MOVN,
+	MIPS1_INS_MOVZ,
+	MIPS1_INS_MSUB,
+	MIPS1_INS_MSUBU,
+	MIPS1_INS_MTC0,
+	MIPS1_INS_MTC1,
+	MIPS1_INS_MTHI,
+	MIPS1_INS_MTLO,
+	MIPS1_INS_MUL,
+	MIPS1_INS_MULT,
+	MIPS1_INS_MULTU,
+	MIPS1_INS_NOR,
+	MIPS1_INS_OR,
+	MIPS1_INS_ORI,
+	MIPS1_INS_SB,
+	MIPS1_INS_SC,
+	MIPS1_INS_SDC1,
+	MIPS1_INS_SH,
+	MIPS1_INS_SLL,
+	MIPS1_INS_SLLV,
+	MIPS1_INS_SLT,
+	MIPS1_INS_SLTI,
+	MIPS1_INS_SLTIU,
+	MIPS1_INS_SLTU,
+	MIPS1_INS_SRA,
+	MIPS1_INS_SRAV,
+	MIPS1_INS_SRL,
+	MIPS1_INS_SRLV,
+	MIPS1_INS_SUB,
+	MIPS1_INS_SUBU,
+	MIPS1_INS_SW,
+	MIPS1_INS_SWC1,
+	MIPS1_INS_SWL,
+	MIPS1_INS_SWR,
+	MIPS1_INS_SYSCALL,
+	MIPS1_INS_TEQ,
+	MIPS1_INS_TEQI,
+	MIPS1_INS_TGE,
+	MIPS1_INS_TGEI,
+	MIPS1_INS_TGEIU,
+	MIPS1_INS_TGEU,
+	MIPS1_INS_TLT,
+	MIPS1_INS_TLTI,
+	MIPS1_INS_TLTIU,
+	MIPS1_INS_TLTU,
+	MIPS1_INS_TNE,
+	MIPS1_INS_TNEI,
+	MIPS1_INS_XOR,
+	MIPS1_INS_XORI,
+	__MIPS1_INS_NULL,
+};
+
+// op code groups
+#define MIPS1_OP_SPECIAL    0b000000
+#define MIPS1_OP_SPECIAL2   0b011100
+#define MIPS1_OP_REGIMM     0b000001
+#define MIPS1_OP_COP0       0b010000
+#define MIPS1_OP_COP1       0b010001
+
+// op codes
+#define MIPS1_OP_ADDI       0b001000
+#define MIPS1_OP_ADDIU      0b001001
+#define MIPS1_OP_ANDI       0b001100
+#define MIPS1_OP_BEQ        0b000100
+#define MIPS1_OP_BGTZ       0b000111
+#define MIPS1_OP_BLEZ       0b000110
+#define MIPS1_OP_BNE        0b000101
+#define MIPS1_OP_J          0b000010
+#define MIPS1_OP_JAL        0b000011
+#define MIPS1_OP_LB         0b100000
+#define MIPS1_OP_LBU        0b100100
+#define MIPS1_OP_LH         0b100001
+#define MIPS1_OP_LHU        0b100101
+#define MIPS1_OP_LL         0b110000
+#define MIPS1_OP_LUI        0b001111
+#define MIPS1_OP_LW         0b100011
+#define MIPS1_OP_LWC1       0b110001
+#define MIPS1_OP_LWL        0b100010
+#define MIPS1_OP_LWR        0b100110
+#define MIPS1_OP_ORI        0b001101
+#define MIPS1_OP_SB         0b101000
+#define MIPS1_OP_SC         0b111000
+#define MIPS1_OP_SDC1       0b111101
+#define MIPS1_OP_SH         0b101001
+#define MIPS1_OP_SLTI       0b001010
+#define MIPS1_OP_SLTIU      0b001011
+#define MIPS1_OP_SW         0b101011
+#define MIPS1_OP_SWC1       0b111001
+#define MIPS1_OP_SWL        0b101010
+#define MIPS1_OP_SWR        0b101110
+#define MIPS1_OP_XORI       0b001110
+
+// op special
+#define MIPS1_FUNCT_ADD     0b100000
+#define MIPS1_FUNCT_ADDU    0b100001
+#define MIPS1_FUNCT_AND     0b100100
+#define MIPS1_FUNCT_BREAK   0b001101
+#define MIPS1_FUNCT_DIV     0b011010
+#define MIPS1_FUNCT_DIVU    0b011011
+#define MIPS1_FUNCT_JALR    0b001001
+#define MIPS1_FUNCT_JR      0b001000
+#define MIPS1_FUNCT_MFHI    0b010000
+#define MIPS1_FUNCT_MFLO    0b010010
+#define MIPS1_FUNCT_MOVN    0b001011
+#define MIPS1_FUNCT_MOVZ    0b001010
+#define MIPS1_FUNCT_MTHI    0b010001
+#define MIPS1_FUNCT_MTLO    0b010011
+#define MIPS1_FUNCT_MULT    0b011000
+#define MIPS1_FUNCT_MULTU   0b011001
+#define MIPS1_FUNCT_NOR     0b100111
+#define MIPS1_FUNCT_OR      0b100101
+#define MIPS1_FUNCT_SLL     0b000000
+#define MIPS1_FUNCT_SLLV    0b000100
+#define MIPS1_FUNCT_SLT     0b101010
+#define MIPS1_FUNCT_SLTU    0b101011
+#define MIPS1_FUNCT_SRA     0b000011
+#define MIPS1_FUNCT_SRAV    0b000111
+#define MIPS1_FUNCT_SRL     0b000010
+#define MIPS1_FUNCT_SRLV    0b000110
+#define MIPS1_FUNCT_SUB     0b100010
+#define MIPS1_FUNCT_SUBU    0b100011
+#define MIPS1_FUNCT_SYSCALL 0b001100
+#define MIPS1_FUNCT_TEQ     0b110100
+#define MIPS1_FUNCT_TGE     0b110000
+#define MIPS1_FUNCT_TGEU    0b110001
+#define MIPS1_FUNCT_TLT     0b110010
+#define MIPS1_FUNCT_TLTU    0b110011
+#define MIPS1_FUNCT_TNE     0b110110
+#define MIPS1_FUNCT_XOR     0b100110
+
+// op special 2
+#define MIPS1_FUNCT_CLO     0b100001
+#define MIPS1_FUNCT_CLZ     0b100000
+#define MIPS1_FUNCT_MADD    0b000000
+#define MIPS1_FUNCT_MADDU   0b000001
+#define MIPS1_FUNCT_MSUB    0b000100
+#define MIPS1_FUNCT_MSUBU   0b000101
+#define MIPS1_FUNCT_MUL     0b100000
+
+// op regimm
+#define MIPS1_FUNCT_BGEZ       0b00001
+#define MIPS1_FUNCT_BGEZAL     0b10001
+#define MIPS1_FUNCT_BLTZ       0b00001
+#define MIPS1_FUNCT_BLTZAL     0b10000
+#define MIPS1_FUNCT_TEQI       0b01100
+#define MIPS1_FUNCT_TGEI       0b01000
+#define MIPS1_FUNCT_TGEIU      0b01001
+#define MIPS1_FUNCT_TLTI       0b01010
+#define MIPS1_FUNCT_TLTIU      0b01011
+#define MIPS1_FUNCT_TNEI       0b01110
+
+// op cop
+#define MIPS1_FUNCT_BC         0b01000
+#define MIPS1_FUNCT_MF         0b00000
+#define MIPS1_FUNCT_MT         0b00100
+
+// sub op c0
+#define MIPS1_FUNCT_ERET       0b011000
+
+#define __MIPS1_INS_LEN	        (__MIPS1_INS_NULL)
+#define __MIPS1_PSEUDO_LEN	(34)
+#define __MIPS1_GRAMMER_LEN	(__MIPS1_INS_LEN + __MIPS1_PSEUDO_LEN)
+
+extern struct mips32_grammer mips1_grammers[__MIPS1_GRAMMER_LEN];
+extern union mips32_instruction mips1_instructions[__MIPS1_INS_LEN];
+
+#endif /* __MIPS1_H__ */
diff --git a/include/mips32r2.h b/include/mips32r2.h
new file mode 100644
index 0000000..dd462e0
--- /dev/null
+++ b/include/mips32r2.h
@@ -0,0 +1,342 @@
+/* Copyright (c) 2024 Freya Murphy */
+
+#ifndef __MIPS32R2_H__
+#define __MIPS32R2_H__
+
+#include <mlimits.h>
+#include <stdint.h>
+#include <mips.h>
+
+// TODO:
+// balc
+
+/* mips instructions */
+enum mips32r2_instruction_type {
+	MIPS32R2_INS_ADD,
+	MIPS32R2_INS_ADDI,
+	MIPS32R2_INS_ADDIU,
+	MIPS32R2_INS_ADDU,
+	MIPS32R2_INS_AND,
+	MIPS32R2_INS_ANDI,
+	MIPS32R2_INS_BC1F,
+	MIPS32R2_INS_BC1FL,
+	MIPS32R2_INS_BC1T,
+	MIPS32R2_INS_BC1TL,
+	MIPS32R2_INS_BC2F,
+	MIPS32R2_INS_BC2FL,
+	MIPS32R2_INS_BC2T,
+	MIPS32R2_INS_BC2TL,
+	MIPS32R2_INS_BEQ,
+	MIPS32R2_INS_BEQL,
+	MIPS32R2_INS_BGEZ,
+	MIPS32R2_INS_BGEZAL,
+	MIPS32R2_INS_BGEZALL,
+	MIPS32R2_INS_BGEZL,
+	MIPS32R2_INS_BGTZ,
+	MIPS32R2_INS_BGTZL,
+	MIPS32R2_INS_BLEZ,
+	MIPS32R2_INS_BLEZL,
+	MIPS32R2_INS_BLTZ,
+	MIPS32R2_INS_BLTZAL,
+	MIPS32R2_INS_BLTZALL,
+	MIPS32R2_INS_BLTZL,
+	MIPS32R2_INS_BNE,
+	MIPS32R2_INS_BNEL,
+	MIPS32R2_INS_BREAK,
+	MIPS32R2_INS_CACHE,
+	MIPS32R2_INS_CFC1,
+	MIPS32R2_INS_CFC2,
+	MIPS32R2_INS_CLO,
+	MIPS32R2_INS_CLZ,
+	MIPS32R2_INS_COP2,
+	MIPS32R2_INS_CTC1,
+	MIPS32R2_INS_CTC2,
+	MIPS32R2_INS_DERET,
+	MIPS32R2_INS_DI,
+	MIPS32R2_INS_DIV,
+	MIPS32R2_INS_DIVU,
+	MIPS32R2_INS_EI,
+	MIPS32R2_INS_ERET,
+	MIPS32R2_INS_EXT,
+	MIPS32R2_INS_INS,
+	MIPS32R2_INS_J,
+	MIPS32R2_INS_JAL,
+	MIPS32R2_INS_JALR,
+	MIPS32R2_INS_JR,
+	MIPS32R2_INS_LB,
+	MIPS32R2_INS_LBU,
+	MIPS32R2_INS_LDC1,
+	MIPS32R2_INS_LDC2,
+	MIPS32R2_INS_LDXC1,
+	MIPS32R2_INS_LH,
+	MIPS32R2_INS_LHU,
+	MIPS32R2_INS_LL,
+	MIPS32R2_INS_LUI,
+	MIPS32R2_INS_LUXC1,
+	MIPS32R2_INS_LW,
+	MIPS32R2_INS_LWC1,
+	MIPS32R2_INS_LWC2,
+	MIPS32R2_INS_LWL,
+	MIPS32R2_INS_LWR,
+	MIPS32R2_INS_LWXC1,
+	MIPS32R2_INS_MADD,
+	MIPS32R2_INS_MADDU,
+	MIPS32R2_INS_MFC0,
+	MIPS32R2_INS_MFC1,
+	MIPS32R2_INS_MFC2,
+	MIPS32R2_INS_MFHC1,
+	MIPS32R2_INS_MFHC2,
+	MIPS32R2_INS_MFHI,
+	MIPS32R2_INS_MFLO,
+	MIPS32R2_INS_MOVF,
+	MIPS32R2_INS_MOVN,
+	MIPS32R2_INS_MOVT,
+	MIPS32R2_INS_MOVZ,
+	MIPS32R2_INS_MSUB,
+	MIPS32R2_INS_MSUBU,
+	MIPS32R2_INS_MTC0,
+	MIPS32R2_INS_MTC1,
+	MIPS32R2_INS_MTC2,
+	MIPS32R2_INS_MTHC1,
+	MIPS32R2_INS_MTHC2,
+	MIPS32R2_INS_MTHI,
+	MIPS32R2_INS_MTLO,
+	MIPS32R2_INS_MUL,
+	MIPS32R2_INS_MULT,
+	MIPS32R2_INS_MULTU,
+	MIPS32R2_INS_NOR,
+	MIPS32R2_INS_OR,
+	MIPS32R2_INS_ORI,
+	MIPS32R2_INS_PREF,
+	MIPS32R2_INS_PREFX,
+	MIPS32R2_INS_RDHWR,
+	MIPS32R2_INS_RDPGPR,
+	MIPS32R2_INS_ROTR,
+	MIPS32R2_INS_ROTRV,
+	MIPS32R2_INS_SB,
+	MIPS32R2_INS_SC,
+	MIPS32R2_INS_SDBBP,
+	MIPS32R2_INS_SDC1,
+	MIPS32R2_INS_SDC2,
+	MIPS32R2_INS_SDXC1,
+	MIPS32R2_INS_SEB,
+	MIPS32R2_INS_SEH,
+	MIPS32R2_INS_SH,
+	MIPS32R2_INS_SLL,
+	MIPS32R2_INS_SLLV,
+	MIPS32R2_INS_SLT,
+	MIPS32R2_INS_SLTI,
+	MIPS32R2_INS_SLTIU,
+	MIPS32R2_INS_SLTU,
+	MIPS32R2_INS_SRA,
+	MIPS32R2_INS_SRAV,
+	MIPS32R2_INS_SRL,
+	MIPS32R2_INS_SRLV,
+	MIPS32R2_INS_SUB,
+	MIPS32R2_INS_SUBU,
+	MIPS32R2_INS_SUXC1,
+	MIPS32R2_INS_SW,
+	MIPS32R2_INS_SWC1,
+	MIPS32R2_INS_SWC2,
+	MIPS32R2_INS_SWL,
+	MIPS32R2_INS_SWR,
+	MIPS32R2_INS_SWXC1,
+	MIPS32R2_INS_SYNC,
+	MIPS32R2_INS_SYNCI,
+	MIPS32R2_INS_SYSCALL,
+	MIPS32R2_INS_TEQ,
+	MIPS32R2_INS_TEQI,
+	MIPS32R2_INS_TGE,
+	MIPS32R2_INS_TGEI,
+	MIPS32R2_INS_TGEIU,
+	MIPS32R2_INS_TGEU,
+	MIPS32R2_INS_TLBP,
+	MIPS32R2_INS_TLBR,
+	MIPS32R2_INS_TLBWI,
+	MIPS32R2_INS_TLBWR,
+	MIPS32R2_INS_TLT,
+	MIPS32R2_INS_TLTI,
+	MIPS32R2_INS_TLTIU,
+	MIPS32R2_INS_TLTU,
+	MIPS32R2_INS_TNE,
+	MIPS32R2_INS_TNEI,
+	MIPS32R2_INS_WAIT,
+	MIPS32R2_INS_WRPGPR,
+	MIPS32R2_INS_WSBH,
+	MIPS32R2_INS_XOR,
+	MIPS32R2_INS_XORI,
+	__MIPS32R2_INS_NULL,
+};
+
+// op code groups
+#define MIPS32R2_OP_SPECIAL    0b000000
+#define MIPS32R2_OP_SPECIAL2   0b011100
+#define MIPS32R2_OP_SPECIAL3   0b011111
+#define MIPS32R2_OP_REGIMM     0b000001
+#define MIPS32R2_OP_COP0       0b010000
+#define MIPS32R2_OP_COP1       0b010001
+#define MIPS32R2_OP_COP2       0b010010
+#define MIPS32R2_OP_COP1X      0b010011
+
+// op codes
+#define MIPS32R2_OP_ADDI       0b001000
+#define MIPS32R2_OP_ADDIU      0b001001
+#define MIPS32R2_OP_ANDI       0b001100
+#define MIPS32R2_OP_BC         0b110010
+#define MIPS32R2_OP_BEQ        0b000100
+#define MIPS32R2_OP_BEQL       0b010100
+#define MIPS32R2_OP_BGTZ       0b000111
+#define MIPS32R2_OP_BGTZL      0b010111
+#define MIPS32R2_OP_BLEZ       0b000110
+#define MIPS32R2_OP_BLEZL      0b010110
+#define MIPS32R2_OP_BNE        0b000101
+#define MIPS32R2_OP_BNEL       0b010101
+#define MIPS32R2_OP_CACHE      0b101111
+#define MIPS32R2_OP_J          0b000010
+#define MIPS32R2_OP_JAL        0b000011
+#define MIPS32R2_OP_JALX       0b011101
+#define MIPS32R2_OP_LB         0b100000
+#define MIPS32R2_OP_LBU        0b100100
+#define MIPS32R2_OP_LDC1       0b110101
+#define MIPS32R2_OP_LDC2       0b110110
+#define MIPS32R2_OP_LH         0b100001
+#define MIPS32R2_OP_LHU        0b100101
+#define MIPS32R2_OP_LL         0b110000
+#define MIPS32R2_OP_LUI        0b001111
+#define MIPS32R2_OP_LW         0b100011
+#define MIPS32R2_OP_LWC1       0b110001
+#define MIPS32R2_OP_LWC2       0b110010
+#define MIPS32R2_OP_LWL        0b100010
+#define MIPS32R2_OP_LWR        0b100110
+#define MIPS32R2_OP_ORI        0b001101
+#define MIPS32R2_OP_PREF       0b110011
+#define MIPS32R2_OP_SB         0b101000
+#define MIPS32R2_OP_SC         0b111000
+#define MIPS32R2_OP_SDC1       0b111101
+#define MIPS32R2_OP_SDC2       0b111110
+#define MIPS32R2_OP_SH         0b101001
+#define MIPS32R2_OP_SLTI       0b001010
+#define MIPS32R2_OP_SLTIU      0b001011
+#define MIPS32R2_OP_SW         0b101011
+#define MIPS32R2_OP_SWC1       0b111001
+#define MIPS32R2_OP_SWC2       0b111010
+#define MIPS32R2_OP_SWL        0b101010
+#define MIPS32R2_OP_SWR        0b101110
+#define MIPS32R2_OP_XORI       0b001110
+
+// op special
+#define MIPS32R2_FUNCT_ADD     0b100000
+#define MIPS32R2_FUNCT_ADDU    0b100001
+#define MIPS32R2_FUNCT_AND     0b100100
+#define MIPS32R2_FUNCT_BREAK   0b001101
+#define MIPS32R2_FUNCT_DIV     0b000011
+#define MIPS32R2_FUNCT_DIVU    0b011011
+#define MIPS32R2_FUNCT_JALR    0b001001
+#define MIPS32R2_FUNCT_JR      0b001000
+#define MIPS32R2_FUNCT_MFHI    0b010000
+#define MIPS32R2_FUNCT_MFLO    0b010010
+#define MIPS32R2_FUNCT_MOVCL   0b000001
+#define MIPS32R2_FUNCT_MOVN    0b001011
+#define MIPS32R2_FUNCT_MOVZ    0b001010
+#define MIPS32R2_FUNCT_MTHI    0b010001
+#define MIPS32R2_FUNCT_MTLO    0b010011
+#define MIPS32R2_FUNCT_MULT    0b011000
+#define MIPS32R2_FUNCT_MULTU   0b011001
+#define MIPS32R2_FUNCT_NOR     0b100111
+#define MIPS32R2_FUNCT_OR      0b100101
+#define MIPS32R2_FUNCT_SLL     0b000000
+#define MIPS32R2_FUNCT_SLLV    0b000100
+#define MIPS32R2_FUNCT_SLT     0b101010
+#define MIPS32R2_FUNCT_SLTU    0b101011
+#define MIPS32R2_FUNCT_SRA     0b000011
+#define MIPS32R2_FUNCT_SRAV    0b000111
+#define MIPS32R2_FUNCT_SRL     0b000010
+#define MIPS32R2_FUNCT_SRLV    0b000110
+#define MIPS32R2_FUNCT_SUB     0b100010
+#define MIPS32R2_FUNCT_SUBU    0b100011
+#define MIPS32R2_FUNCT_SYNC    0b001111
+#define MIPS32R2_FUNCT_SYSCALL 0b001100
+#define MIPS32R2_FUNCT_TEQ     0b110100
+#define MIPS32R2_FUNCT_TGE     0b110000
+#define MIPS32R2_FUNCT_TGEU    0b110001
+#define MIPS32R2_FUNCT_TLT     0b110010
+#define MIPS32R2_FUNCT_TLTU    0b110011
+#define MIPS32R2_FUNCT_TNE     0b110110
+#define MIPS32R2_FUNCT_XOR     0b100110
+
+// op special2
+#define MIPS32R2_FUNCT_CLO     0b100001
+#define MIPS32R2_FUNCT_CLZ     0b100000
+#define MIPS32R2_FUNCT_MADD    0b000000
+#define MIPS32R2_FUNCT_MADDU   0b000001
+#define MIPS32R2_FUNCT_MSUB    0b000100
+#define MIPS32R2_FUNCT_MSUBU   0b000101
+#define MIPS32R2_FUNCT_MUL     0b000010
+#define MIPS32R2_FUNCT_SDBBP   0b111111
+
+// op special 3
+#define MIPS32R2_FUNCT_EXT     0b000000
+#define MIPS32R2_FUNCT_INS     0b000100
+#define MIPS32R2_FUNCT_RDHWR   0b111011
+#define MIPS32R2_FUNCT_BSHFL   0b100000
+
+// op bshfl
+#define MIPS32R2_FUNCT_SEB     0b10000
+#define MIPS32R2_FUNCT_SEH     0b11000
+#define MIPS32R2_FUNCT_WSBH    0b00010
+
+// op regimm
+#define MIPS32R2_FUNCT_BGEZ    0b00001
+#define MIPS32R2_FUNCT_BGEZAL  0b10001
+#define MIPS32R2_FUNCT_BGEZALL 0b10011
+#define MIPS32R2_FUNCT_BGEZL   0b00011
+#define MIPS32R2_FUNCT_BLTZ    0b00000
+#define MIPS32R2_FUNCT_BLTZAL  0b10000
+#define MIPS32R2_FUNCT_BLTZALL 0b10010
+#define MIPS32R2_FUNCT_BLTZL   0b00010
+#define MIPS32R2_FUNCT_SYNCI   0b11111
+#define MIPS32R2_FUNCT_TEQI    0b01100
+#define MIPS32R2_FUNCT_TGEI    0b01000
+#define MIPS32R2_FUNCT_TGEIU   0b01001
+#define MIPS32R2_FUNCT_TLTI    0b01010
+#define MIPS32R2_FUNCT_TLTIU   0b01011
+#define MIPS32R2_FUNCT_TNEI    0b01110
+
+// op cop cfunct
+#define MIPS32R2_FUNCT_BC      0b01000
+#define MIPS32R2_FUNCT_CF      0b00010
+#define MIPS32R2_FUNCT_CT      0b00110
+#define MIPS32R2_FUNCT_MF      0b00000
+#define MIPS32R2_FUNCT_MFH     0b00011
+#define MIPS32R2_FUNCT_MT      0b00100
+#define MIPS32R2_FUNCT_MTH     0b00111
+#define MIPS32R2_FUNCT_MFMC0   0b01011
+#define MIPS32R2_FUNCT_RDPGPR  0b01010
+#define MIPS32R2_FUNCT_WRPGPR  0b01110
+
+// op cop funct
+#define MIPS32R2_FUNCT_DERET   0b011111
+#define MIPS32R2_FUNCT_ERET    0b011000
+#define MIPS32R2_FUNCT_TLBP    0b001000
+#define MIPS32R2_FUNCT_TLBR    0b000001
+#define MIPS32R2_FUNCT_TLBWI   0b000010
+#define MIPS32R2_FUNCT_TLBWR   0b000110
+
+// op cop1x
+#define MIPS32R2_FUNCT_LDXC1   0b000001
+#define MIPS32R2_FUNCT_LUXC1   0b000101
+#define MIPS32R2_FUNCT_LWXC1   0b000000
+#define MIPS32R2_FUNCT_PREFX   0b001111
+#define MIPS32R2_FUNCT_SDXC1   0b001001
+#define MIPS32R2_FUNCT_SUXC1   0b001101
+#define MIPS32R2_FUNCT_SWXC1   0b001000
+#define MIPS32R2_FUNCT_WAIT    0b100000
+
+#define __MIPS32R2_INS_LEN	(__MIPS32R2_INS_NULL)
+#define __MIPS32R2_PSEUDO_LEN	(38)
+#define __MIPS32R2_GRAMMER_LEN	(__MIPS32R2_INS_LEN + __MIPS32R2_PSEUDO_LEN)
+
+extern struct mips32_grammer mips32r2_grammers[__MIPS32R2_GRAMMER_LEN];
+extern union mips32_instruction mips32r2_instructions[__MIPS32R2_INS_LEN];
+
+#endif /* __MIPS32R2_H__ */
diff --git a/include/mips32r6.h b/include/mips32r6.h
index c2aad2d..88eda4d 100644
--- a/include/mips32r6.h
+++ b/include/mips32r6.h
@@ -5,7 +5,7 @@
 
 #include <mlimits.h>
 #include <stdint.h>
-#include <mips32.h>
+#include <mips.h>
 
 /* mips instructions */
 enum mips32r6_instruction_type {