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/* Copyright (c) 2024 Freya Murphy */

#ifndef __MIPS1_H__
#define __MIPS1_H__

#include <mlimits.h>
#include <stdint.h>
#include <mips.h>

// TODO:
// CFC1
// CTC1
// COP0-3
// LWC1-3
// SWC1-3

/* mips instructions */
enum mips1_instruction_type {
	MIPS1_INS_ADD,
	MIPS1_INS_ADDI,
	MIPS1_INS_ADDIU,
	MIPS1_INS_ADDU,
	MIPS1_INS_AND,
	MIPS1_INS_ANDI,
	MIPS1_INS_BC1F,
	MIPS1_INS_BC1T,
	MIPS1_INS_BEQ,
	MIPS1_INS_BGEZ,
	MIPS1_INS_BGEZAL,
	MIPS1_INS_BGTZ,
	MIPS1_INS_BLEZ,
	MIPS1_INS_BLTZAL,
	MIPS1_INS_BLTZ,
	MIPS1_INS_BNE,
	MIPS1_INS_BREAK,
	MIPS1_INS_CLO,
	MIPS1_INS_CLZ,
	MIPS1_INS_DIV,
	MIPS1_INS_DIVU,
	MIPS1_INS_ERET,
	MIPS1_INS_J,
	MIPS1_INS_JAL,
	MIPS1_INS_JALR,
	MIPS1_INS_JR,
	MIPS1_INS_LB,
	MIPS1_INS_LBU,
	MIPS1_INS_LH,
	MIPS1_INS_LHU,
	MIPS1_INS_LL,
	MIPS1_INS_LUI,
	MIPS1_INS_LW,
	MIPS1_INS_LWC1,
	MIPS1_INS_LWL,
	MIPS1_INS_LWR,
	MIPS1_INS_MADD,
	MIPS1_INS_MADDU,
	MIPS1_INS_MFC0,
	MIPS1_INS_MFC1,
	MIPS1_INS_MFHI,
	MIPS1_INS_MFLO,
	MIPS1_INS_MOVN,
	MIPS1_INS_MOVZ,
	MIPS1_INS_MSUB,
	MIPS1_INS_MSUBU,
	MIPS1_INS_MTC0,
	MIPS1_INS_MTC1,
	MIPS1_INS_MTHI,
	MIPS1_INS_MTLO,
	MIPS1_INS_MUL,
	MIPS1_INS_MULT,
	MIPS1_INS_MULTU,
	MIPS1_INS_NOR,
	MIPS1_INS_OR,
	MIPS1_INS_ORI,
	MIPS1_INS_SB,
	MIPS1_INS_SC,
	MIPS1_INS_SDC1,
	MIPS1_INS_SH,
	MIPS1_INS_SLL,
	MIPS1_INS_SLLV,
	MIPS1_INS_SLT,
	MIPS1_INS_SLTI,
	MIPS1_INS_SLTIU,
	MIPS1_INS_SLTU,
	MIPS1_INS_SRA,
	MIPS1_INS_SRAV,
	MIPS1_INS_SRL,
	MIPS1_INS_SRLV,
	MIPS1_INS_SUB,
	MIPS1_INS_SUBU,
	MIPS1_INS_SW,
	MIPS1_INS_SWC1,
	MIPS1_INS_SWL,
	MIPS1_INS_SWR,
	MIPS1_INS_SYSCALL,
	MIPS1_INS_TEQ,
	MIPS1_INS_TEQI,
	MIPS1_INS_TGE,
	MIPS1_INS_TGEI,
	MIPS1_INS_TGEIU,
	MIPS1_INS_TGEU,
	MIPS1_INS_TLT,
	MIPS1_INS_TLTI,
	MIPS1_INS_TLTIU,
	MIPS1_INS_TLTU,
	MIPS1_INS_TNE,
	MIPS1_INS_TNEI,
	MIPS1_INS_XOR,
	MIPS1_INS_XORI,
	__MIPS1_INS_NULL,
};

// op code groups
#define MIPS1_OP_SPECIAL    0b000000
#define MIPS1_OP_SPECIAL2   0b011100
#define MIPS1_OP_REGIMM     0b000001
#define MIPS1_OP_COP0       0b010000
#define MIPS1_OP_COP1       0b010001

// op codes
#define MIPS1_OP_ADDI       0b001000
#define MIPS1_OP_ADDIU      0b001001
#define MIPS1_OP_ANDI       0b001100
#define MIPS1_OP_BEQ        0b000100
#define MIPS1_OP_BGTZ       0b000111
#define MIPS1_OP_BLEZ       0b000110
#define MIPS1_OP_BNE        0b000101
#define MIPS1_OP_J          0b000010
#define MIPS1_OP_JAL        0b000011
#define MIPS1_OP_LB         0b100000
#define MIPS1_OP_LBU        0b100100
#define MIPS1_OP_LH         0b100001
#define MIPS1_OP_LHU        0b100101
#define MIPS1_OP_LL         0b110000
#define MIPS1_OP_LUI        0b001111
#define MIPS1_OP_LW         0b100011
#define MIPS1_OP_LWC1       0b110001
#define MIPS1_OP_LWL        0b100010
#define MIPS1_OP_LWR        0b100110
#define MIPS1_OP_ORI        0b001101
#define MIPS1_OP_SB         0b101000
#define MIPS1_OP_SC         0b111000
#define MIPS1_OP_SDC1       0b111101
#define MIPS1_OP_SH         0b101001
#define MIPS1_OP_SLTI       0b001010
#define MIPS1_OP_SLTIU      0b001011
#define MIPS1_OP_SW         0b101011
#define MIPS1_OP_SWC1       0b111001
#define MIPS1_OP_SWL        0b101010
#define MIPS1_OP_SWR        0b101110
#define MIPS1_OP_XORI       0b001110

// op special
#define MIPS1_FUNCT_ADD     0b100000
#define MIPS1_FUNCT_ADDU    0b100001
#define MIPS1_FUNCT_AND     0b100100
#define MIPS1_FUNCT_BREAK   0b001101
#define MIPS1_FUNCT_DIV     0b011010
#define MIPS1_FUNCT_DIVU    0b011011
#define MIPS1_FUNCT_JALR    0b001001
#define MIPS1_FUNCT_JR      0b001000
#define MIPS1_FUNCT_MFHI    0b010000
#define MIPS1_FUNCT_MFLO    0b010010
#define MIPS1_FUNCT_MOVN    0b001011
#define MIPS1_FUNCT_MOVZ    0b001010
#define MIPS1_FUNCT_MTHI    0b010001
#define MIPS1_FUNCT_MTLO    0b010011
#define MIPS1_FUNCT_MULT    0b011000
#define MIPS1_FUNCT_MULTU   0b011001
#define MIPS1_FUNCT_NOR     0b100111
#define MIPS1_FUNCT_OR      0b100101
#define MIPS1_FUNCT_SLL     0b000000
#define MIPS1_FUNCT_SLLV    0b000100
#define MIPS1_FUNCT_SLT     0b101010
#define MIPS1_FUNCT_SLTU    0b101011
#define MIPS1_FUNCT_SRA     0b000011
#define MIPS1_FUNCT_SRAV    0b000111
#define MIPS1_FUNCT_SRL     0b000010
#define MIPS1_FUNCT_SRLV    0b000110
#define MIPS1_FUNCT_SUB     0b100010
#define MIPS1_FUNCT_SUBU    0b100011
#define MIPS1_FUNCT_SYSCALL 0b001100
#define MIPS1_FUNCT_TEQ     0b110100
#define MIPS1_FUNCT_TGE     0b110000
#define MIPS1_FUNCT_TGEU    0b110001
#define MIPS1_FUNCT_TLT     0b110010
#define MIPS1_FUNCT_TLTU    0b110011
#define MIPS1_FUNCT_TNE     0b110110
#define MIPS1_FUNCT_XOR     0b100110

// op special 2
#define MIPS1_FUNCT_CLO     0b100001
#define MIPS1_FUNCT_CLZ     0b100000
#define MIPS1_FUNCT_MADD    0b000000
#define MIPS1_FUNCT_MADDU   0b000001
#define MIPS1_FUNCT_MSUB    0b000100
#define MIPS1_FUNCT_MSUBU   0b000101
#define MIPS1_FUNCT_MUL     0b100000

// op regimm
#define MIPS1_FUNCT_BGEZ       0b00001
#define MIPS1_FUNCT_BGEZAL     0b10001
#define MIPS1_FUNCT_BLTZ       0b00001
#define MIPS1_FUNCT_BLTZAL     0b10000
#define MIPS1_FUNCT_TEQI       0b01100
#define MIPS1_FUNCT_TGEI       0b01000
#define MIPS1_FUNCT_TGEIU      0b01001
#define MIPS1_FUNCT_TLTI       0b01010
#define MIPS1_FUNCT_TLTIU      0b01011
#define MIPS1_FUNCT_TNEI       0b01110

// op cop
#define MIPS1_FUNCT_BC         0b01000
#define MIPS1_FUNCT_MF         0b00000
#define MIPS1_FUNCT_MT         0b00100

// sub op c0
#define MIPS1_FUNCT_ERET       0b011000

#define __MIPS1_INS_LEN	        (__MIPS1_INS_NULL)
#define __MIPS1_PSEUDO_LEN	(34)
#define __MIPS1_GRAMMER_LEN	(__MIPS1_INS_LEN + __MIPS1_PSEUDO_LEN)

extern struct mips32_grammer mips1_grammers[__MIPS1_GRAMMER_LEN];
extern union mips32_instruction mips1_instructions[__MIPS1_INS_LEN];

#endif /* __MIPS1_H__ */