refactor, new arch dirs, (wip) page alloc on write, hsv screen (convert to userspace later), other fixes

5 files changed, 407 insertions, 0 deletions

diff --git a/src/arch/amd64/drivers/bochs.c b/src/arch/amd64/drivers/bochs.c
new file mode 100644
index 0000000..5383213
--- /dev/null
+++ b/src/arch/amd64/drivers/bochs.c
@@ -0,0 +1,73 @@
+#include <lib.h>
+#include <memory.h>
+#include <stdint.h>
+#include <panic.h>
+#include <pci.h>
+#include <bochs.h>
+
+#include "../bindings.h"
+
+#define INDEX           0x1CE
+#define DATA            0x1CF
+
+#define INDEX_ID            0
+#define INDEX_XRES          1
+#define INDEX_YRES          2
+#define INDEX_BPP           3
+#define INDEX_ENABLE        4
+#define INDEX_BANK          5
+#define INDEX_VIRT_WIDTH    6
+#define INDEX_VIRT_HEIGHT   7
+#define INDEX_X_OFFSET      8
+#define INDEX_Y_OFFSET      9
+
+#define DATA_DISP_DISABLE   0x00
+#define DATA_DISP_ENABLE    0x01
+#define DATA_LFB_ENABLE     0x40
+#define DATA_NO_CLEAR_MEM   0x80
+
+#define BOCHS_PCI_VENDOR    0x1234
+#define BOCHS_PCI_DEVICE    0x1111
+
+static void write(uint16_t index, uint16_t data) {
+    outw(INDEX, index);
+    outw(DATA, data);
+}
+
+static uint16_t read(uint16_t value) {
+    outw(INDEX, value);
+    return inw(DATA);
+}
+
+static int is_available(void) {
+    return (read(INDEX_ID) == 0xB0C5);
+}
+
+static void set_mode(uint16_t width, uint16_t height, uint16_t bit_depth, int lfb, int clear) {
+    write(INDEX_ENABLE, DATA_DISP_DISABLE);
+    write(INDEX_XRES, width);
+    write(INDEX_YRES, height);
+    write(INDEX_BPP, bit_depth);
+    write(INDEX_ENABLE, DATA_DISP_ENABLE |
+        (lfb ? DATA_LFB_ENABLE : 0) |
+        (clear ? 0 : DATA_NO_CLEAR_MEM));
+}
+
+uint32_t* bochs_init(uint16_t width, uint16_t height, uint8_t bit_depth) {
+
+	set_mode(width, height, bit_depth, true, true);
+
+	if (!is_available())
+        return NULL;
+
+    struct pci_device bochs = {0};
+    bool found = pci_findby_id(&bochs, BOCHS_PCI_DEVICE, BOCHS_PCI_VENDOR, NULL);
+    if (!found)
+        return NULL;
+
+    uint32_t bar0 = pci_rcfg_d(bochs, PCI_BAR0_D);
+    uint32_t *addr = (uint32_t*) (uintptr_t) bar0;
+    addr = mmap(addr, width * height * bit_depth);
+
+    return addr;
+}
diff --git a/src/arch/amd64/drivers/pci.c b/src/arch/amd64/drivers/pci.c
new file mode 100644
index 0000000..410eb7e
--- /dev/null
+++ b/src/arch/amd64/drivers/pci.c
@@ -0,0 +1,166 @@
+#include <stdint.h>
+#include <pci.h>
+#include <panic.h>
+#include <lib.h>
+
+#include "../bindings.h"
+
+#define CONF_ADDR 0xCF8
+#define CONF_DATA 0xCFC
+
+#define TABLE_LEN 16
+
+struct pci_table_entry {
+	struct pci_device device;
+	uint16_t device_id;
+	uint16_t vendor_id;
+	uint8_t class;
+	uint8_t subclass;
+	uint8_t prog_if;
+	uint8_t revision;
+};
+
+static struct pci_table_entry pci_table[TABLE_LEN];
+static size_t pci_table_next = 0;
+
+uint32_t pci_rcfg_d(struct pci_device dev, uint8_t offset) {
+	uint32_t addr = 0x80000000;
+	addr |= ((uint32_t)dev.bus) << 16;
+	addr |= ((uint32_t)dev.device) << 11;
+	addr |= ((uint32_t)dev.function) << 8;
+	addr |= offset & 0xFC;
+
+	outl(CONF_ADDR, addr);
+	uint32_t in = inl(CONF_DATA);
+	return in;
+}
+
+uint16_t pci_rcfg_w(struct pci_device dev, uint8_t offset) {
+	uint32_t dword = pci_rcfg_d(dev, offset);
+	return (uint16_t)((dword >> ((offset & 2) * 8)) & 0xFFFF);
+}
+
+uint8_t pci_rcfg_b(struct pci_device dev, uint8_t offset) {
+	uint32_t dword = pci_rcfg_d(dev, offset);
+	return (uint8_t)((dword >> ((offset & 3) * 8)) & 0xFF);
+}
+
+void pci_wcfg_d(struct pci_device dev, uint8_t offset, uint32_t dword) {
+	uint32_t addr = 0x80000000;
+	addr |= ((uint32_t)dev.bus) << 16;
+	addr |= ((uint32_t)dev.device) << 11;
+	addr |= ((uint32_t)dev.function) << 8;
+	addr |= offset & 0xFC;
+
+	outl(CONF_ADDR, addr);
+	outl(CONF_DATA, dword);
+}
+
+void pci_wcfg_w(struct pci_device dev, uint8_t offset, uint16_t word) {
+	size_t shift = (offset & 2) * 8;
+	uint32_t dword = pci_rcfg_d(dev, offset);
+	dword &= ~(0xFFFF << shift);
+	dword |= word << shift;
+	pci_wcfg_d(dev, offset, dword);
+}
+
+void pci_wcfg_b(struct pci_device dev, uint8_t offset, uint8_t byte) {
+	size_t shift = (offset & 3) * 8;
+	uint32_t dword = pci_rcfg_d(dev, offset);
+	dword &= ~(0xFF << shift);
+	dword |= byte << shift;
+	pci_wcfg_d(dev, offset, dword);
+}
+
+static void print_device(struct pci_table_entry *entry) {
+	kprintf(
+		"BUS: %#-4x  DEV: %#-4x  FUNC: %#-4x  ID: %04x:%04x  CLASS: %02x:%02x:%02x  REV: %#02x\n",
+		entry->device.bus,
+		entry->device.device,
+		entry->device.function,
+		entry->vendor_id,
+		entry->device_id,
+		entry->class,
+		entry->subclass,
+		entry->prog_if,
+		entry->revision
+	);
+}
+
+static struct pci_table_entry *load_device(struct pci_device dev) {
+	if(pci_table_next >= TABLE_LEN)	panic("Too many PCI devices: limit is %d", TABLE_LEN);
+	struct pci_table_entry *entry = &pci_table[pci_table_next++];
+	entry->device = dev;
+	uint32_t dword0 = pci_rcfg_d(dev, 0);
+	uint32_t dword2 = pci_rcfg_d(dev, 8);
+
+	entry->device_id = (dword0 >> 16) & 0xFFFF;
+	entry->vendor_id = dword0 & 0xFFFF;
+
+	entry->class = (dword2 >> 24) & 0xFF;
+	entry->subclass = (dword2 >> 16) & 0xFF;
+	entry->prog_if = (dword2 >> 8) & 0xFF;
+	entry->revision = dword2 & 0xFF;
+
+	return entry;
+}
+
+void pci_init(void) {
+	pci_table_next = 0;
+	struct pci_device pcidev;
+	for(int bus = 0; bus < 256; bus++) {
+		pcidev.bus = bus;
+		for(int dev = 0; dev < 32; dev++) {
+			pcidev.device = dev;
+			pcidev.function = 0;
+
+			uint16_t vendor = pci_rcfg_w(pcidev, 0);
+			if(vendor == 0xFFFF) continue;
+
+			load_device(pcidev);
+
+			uint8_t header_type = pci_rcfg_b(pcidev, 14);
+
+			if(!(header_type & 0x80)) continue;
+			for(int func = 1; func < 8; func++) {
+				pcidev.function = func;
+
+				uint16_t vendor = pci_rcfg_w(pcidev, 0);
+				if(vendor == 0xFFFF) continue;
+
+				load_device(pcidev);
+			}
+		}
+	}
+	kprintf("PCI DEVICES\n");
+	for (size_t i = 0; i < pci_table_next; i++) {
+		print_device(&pci_table[i]);
+	}
+	kprintf("\n");
+}
+
+bool pci_findby_class(struct pci_device *dest, uint8_t class, uint8_t subclass, size_t *offset) {
+	size_t o = 0;
+	if(offset == NULL) offset = &o;
+	for(; *offset < pci_table_next; (*offset)++) {
+		struct pci_table_entry *entry = &pci_table[*offset];
+		if(entry->class == class && entry->subclass == subclass) {
+			*dest = entry->device;
+			return true;
+		}
+	}
+	return false;
+}
+
+bool pci_findby_id(struct pci_device *dest, uint16_t device, uint16_t vendor, size_t *offset) {
+	size_t o = 0;
+	if(offset == NULL) offset = &o;
+	for(; *offset < pci_table_next; (*offset)++) {
+		struct pci_table_entry *entry = &pci_table[*offset];
+		if(entry->device_id == device && entry->vendor_id == vendor) {
+			*dest = entry->device;
+			return true;
+		}
+	}
+	return false;
+}
diff --git a/src/arch/amd64/drivers/pic.c b/src/arch/amd64/drivers/pic.c
new file mode 100644
index 0000000..be7716f
--- /dev/null
+++ b/src/arch/amd64/drivers/pic.c
@@ -0,0 +1,89 @@
+#include "../bindings.h"
+#include "pic.h"
+
+#define PIC1            0x20        /* IO base address for master PIC */
+#define PIC2            0xA0        /* IO base address for slave PIC */
+#define PIC1_COMMAND    PIC1
+#define PIC1_DATA       (PIC1+1)
+#define PIC2_COMMAND    PIC2
+#define PIC2_DATA       (PIC2+1)
+
+#define PIC_EOI         0x20        /* End-of-interrupt command code */
+
+#define ICW1_ICW4       0x01        /* Indicates that ICW4 will be present */
+#define ICW1_SINGLE     0x02        /* Single (cascade) mode */
+#define ICW1_INTERVAL4  0x04        /* Call address interval 4 (8) */
+#define ICW1_LEVEL      0x08        /* Level triggered (edge) mode */
+#define ICW1_INIT       0x10        /* Initialization - required! */
+
+#define ICW4_8086       0x01        /* 8086/88 (MCS-80/85) mode */
+#define ICW4_AUTO       0x02        /* Auto (normal) EOI */
+#define ICW4_BUF_SLAVE  0x08        /* Buffered mode/slave */
+#define ICW4_BUF_MASTER 0x0C        /* Buffered mode/master */
+#define ICW4_SFNM       0x10        /* Special fully nested (not) */
+
+void pic_remap(void) {
+	uint8_t a1, a2;
+
+	a1 = inb(PIC1_DATA);                        // save masks
+	a2 = inb(PIC2_DATA);
+
+	outb(PIC1_COMMAND, ICW1_INIT | ICW1_ICW4);  // starts the initialization sequence (in cascade mode)
+	io_wait();
+	outb(PIC2_COMMAND, ICW1_INIT | ICW1_ICW4);
+	io_wait();
+	outb(PIC1_DATA, PIC_REMAP_OFFSET);          // ICW2: Master PIC vector offset
+	io_wait();
+	outb(PIC2_DATA, PIC_REMAP_OFFSET + 8);      // ICW2: Slave PIC vector offset
+	io_wait();
+	outb(PIC1_DATA, 4);                         // ICW3: tell Master PIC that there is a slave PIC at IRQ2 (0000 0100)
+	io_wait();
+	outb(PIC2_DATA, 2);                         // ICW3: tell Slave PIC its cascade identity (0000 0010)
+	io_wait();
+
+	outb(PIC1_DATA, ICW4_8086);                 // ICW4: have the PICs use 8086 mode (and not 8080 mode)
+	io_wait();
+	outb(PIC2_DATA, ICW4_8086);
+	io_wait();
+
+	outb(PIC1_DATA, a1);   // restore saved masks.
+	outb(PIC2_DATA, a2);
+}
+
+void pic_mask(int irq) {
+	uint16_t port;
+	uint8_t mask;
+	if (irq < 8) {
+		port = PIC1_DATA;
+	} else {
+		port = PIC2_DATA;
+		irq -= 8;
+	}
+	mask = inb(port) | (1 << irq);
+	outb(port, mask);
+}
+
+void pic_unmask(int irq) {
+	uint16_t port;
+	uint8_t mask;
+	if (irq < 8) {
+		port = PIC1_DATA;
+	} else {
+		irq -= 8;
+		port = PIC2_DATA;
+	}
+	mask = inb(port) & ~(1 << irq);
+	outb(port, mask);
+}
+
+void pic_disable(void) {
+	outb(PIC1_DATA, 0xff);
+	outb(PIC2_DATA, 0xff);
+}
+
+void pic_eoi(int irq) {
+	if (irq >= 8) {
+		outb(PIC2_COMMAND, PIC_EOI);
+	}
+	outb(PIC1_COMMAND, PIC_EOI);
+}
diff --git a/src/arch/amd64/drivers/pic.h b/src/arch/amd64/drivers/pic.h
new file mode 100644
index 0000000..2a4670e
--- /dev/null
+++ b/src/arch/amd64/drivers/pic.h
@@ -0,0 +1,31 @@
+#pragma once
+
+#define PIC_REMAP_OFFSET 0x20
+
+/**
+ * Remaps the pie, i.e. initializes it
+ */
+void pic_remap(void);
+
+/**
+ * Masks an external irq to stop firing until un masked
+ * @param irq - the irq to mask
+ */
+void pic_mask(int irq);
+
+/**
+ * Unmasks an external irq to allow interrupts to continue for that irq
+ * @param irq - the irq to unmask
+ */
+void pic_unmask(int irq);
+
+/**
+ * Disabled the pick
+ */
+void pic_disable(void);
+
+/**
+ * Tells the pick that the interrupt has ended
+ * @param irq - the irq that has ended
+ */
+void pic_eoi(int irq);
diff --git a/src/arch/amd64/drivers/serial.c b/src/arch/amd64/drivers/serial.c
new file mode 100644
index 0000000..b9e351e
--- /dev/null
+++ b/src/arch/amd64/drivers/serial.c
@@ -0,0 +1,48 @@
+#include <serial.h>
+
+#include "../bindings.h"
+
+#define PORT 0x3F8
+
+// initialize the specified COM port for serial
+// see https://wiki.osdev.org/Serial_Ports
+// and https://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming
+int serial_init(void) {
+	outb(PORT + 1, 0x00); // disable interrupts
+	outb(PORT + 3, 0x80); // enable DLAB (divisor latch access bit)
+	outb(PORT + 0, 0x03); // (lo) Set baud divisor to 3 38400 baud
+	outb(PORT + 1, 0x00); // (hi)
+	outb(PORT + 3, 0x03); // disable DLAB, set 8 bits per word, one stop bit, no parity
+	outb(PORT + 2, 0xC7); // enable and clear FIFOs, set to maximum threshold
+	// outb(port + 4, 0x0B); // TODO copied this from osdev wiki but i don't think you need it here
+	outb(PORT + 4, 0x1E); // set in loopback mode for test
+	outb(PORT + 0, 0xAE); // test by sending 0xAE
+
+	uint8_t response = inb(PORT + 0);
+	if (response != 0xAE) {
+		// TODO panic here?
+		return -1;
+	}
+
+	// disable loopback, enable IRQs
+	outb(PORT + 4, 0x0F);
+	return 0;
+}
+
+uint8_t serial_in(void) {
+	// wait for data to be available
+	while ((inb(PORT + 5) & 0x01) == 0);
+	return inb(PORT);
+}
+
+void serial_out(uint8_t ch) {
+	// wait for output to be free
+	while ((inb(PORT + 5) & 0x20) == 0);
+	outb(PORT, ch);
+}
+
+void serial_out_str(const char *str) {
+	for (; *str != '\0'; str++) {
+		serial_out(*str);
+	}
+}