initial checkout from wrc

6 files changed, 1389 insertions, 0 deletions

diff --git a/include/x86/arch.h b/include/x86/arch.h
new file mode 100644
index 0000000..113c76b
--- /dev/null
+++ b/include/x86/arch.h
@@ -0,0 +1,303 @@
+/*
+** @file    arch.h
+**
+** @author  Warren R. Carithers
+** @author	K. Reek
+**
+** Definitions of constants and macros for use
+** with the x86 architecture and registers.
+**
+*/
+
+#ifndef X86ARCH_H_
+#define X86ARCH_H_
+
+/*
+** Video stuff
+*/
+#define VID_BASE_ADDR   0xB8000
+
+/*
+** Memory management
+*/
+#define SEG_PRESENT     0x80
+#define SEG_PL_0        0x00
+#define SEG_PL_1        0x20
+#define SEG_PL_2        0x40
+#define SEG_PL_3        0x50
+#define SEG_SYSTEM      0x00
+#define SEG_NON_SYSTEM  0x10
+#define SEG_32BIT       0x04
+#define DESC_IGATE      0x06
+
+/*
+** Exceptions
+*/
+#define N_EXCEPTIONS    256
+
+/*
+** Bit definitions in registers
+**
+** See IA-32 Intel Architecture SW Dev. Manual, Volume 3: System
+** Programming Guide, page 2-8.
+*/
+
+/*
+** EFLAGS
+*/
+#define EFL_RSVD 0xffc00000  /* reserved */
+#define EFL_MB0  0x00008020  /* must be zero */
+#define EFL_MB1  0x00000002  /* must be 1 */
+
+#define EFL_ID   0x00200000
+#define EFL_VIP  0x00100000
+#define EFL_VIF  0x00080000
+#define EFL_AC   0x00040000
+#define EFL_VM   0x00020000
+#define EFL_RF   0x00010000
+#define EFL_NT   0x00004000
+#define EFL_IOPL 0x00003000
+#define EFL_OF   0x00000800
+#define EFL_DF   0x00000400
+#define EFL_IF   0x00000200
+#define EFL_TF   0x00000100
+#define EFL_SF   0x00000080
+#define EFL_ZF   0x00000040
+#define EFL_AF   0x00000010
+#define EFL_PF   0x00000004
+#define EFL_CF   0x00000001
+
+/*
+** CR0, CR1, CR2, CR3, CR4
+**
+** IA-32 V3, page 2-12.
+*/
+#define CR0_RSVD        0x1ffaffc0
+#define CR0_PG          0x80000000
+#define CR0_CD          0x40000000
+#define CR0_NW          0x20000000
+#define CR0_AM          0x00040000
+#define CR0_WP          0x00010000
+#define CR0_NE          0x00000020
+#define CR0_ET          0x00000010
+#define CR0_TS          0x00000008
+#define CR0_EM          0x00000004
+#define CR0_MP          0x00000002
+#define CR0_PE          0x00000001
+
+#define CR1_RSVD        0xffffffff
+
+#define CR2_RSVD        0x00000000
+#define CR2_PF_LIN_ADDR 0xffffffff
+
+#define CR3_RSVD        0x00000fe7
+#define CR3_PD_BASE     0xfffff000
+#define CR3_PCD         0x00000010
+#define CR3_PWT         0x00000008
+
+#define CR4_RSVD        0xfd001000
+#define CR4_UINT        0x02000000
+#define CR4_PKS         0x01000000
+#define CR4_CET         0x00800000
+#define CR4_PKE         0x00400000
+#define CR4_SMAP        0x00200000
+#define CR4_SMEP        0x00100000
+#define CR4_KL          0x00080000
+#define CR4_OSXS        0x00040000
+#define CR4_PCID        0x00020000
+#define CR4_FSGS        0x00010000
+#define CR4_SMXE        0x00004000
+#define CR4_VMXE        0x00002000
+#define CR4_LA57        0x00001000
+#define CR4_UMIP        0x00000800
+#define CR4_OSXMMEXCPT  0x00000400
+#define CR4_OSFXSR      0x00000200
+#define CR4_PCE         0x00000100
+#define CR4_PGE         0x00000080
+#define CR4_MCE         0x00000040
+#define CR4_PAE         0x00000020
+#define CR4_PSE         0x00000010
+#define CR4_DE          0x00000008
+#define CR4_TSD         0x00000004
+#define CR4_PVI         0x00000002
+#define CR4_VME         0x00000001
+
+/*
+** PMode segment selector field masks
+**
+** IA-32 V3, page 3-8.
+*/
+#define SEG_SEL_IX_MASK     0xfff8
+#define SEG_SEL_TI_MASK     0x0004
+#define SEG_SEL_RPL_MASK    0x0003
+
+/*
+** Segment descriptor bytes
+**
+** IA-32 V3, page 3-10.
+**
+** Bytes:
+**    0, 1: segment limit 15:0
+**    2, 3: base address 15:0
+**    4:    base address 23:16
+**    7:    base address 31:24
+*/
+
+/*
+** Byte 5:    access control bits
+**    7:    present
+**    6-5:  DPL
+**    4:    system/user
+**    3-0:  type
+*/
+#define SEG_ACCESS_P_MASK       0x80
+#   define SEG_PRESENT          0x80
+#   define SEG_NOT_PRESENT      0x00
+
+#define SEG_ACCESS_DPL_MASK     0x60
+#   define SEG_DPL_0            0x00
+#   define SEG_DPL_1            0x20
+#   define SEG_DPL_2            0x40
+#   define SEG_DPL_3            0x60
+
+#define SEG_ACCESS_S_MASK       0x10
+#   define SEG_SYSTEM           0x00
+#   define SEG_NON_SYSTEM       0x10
+
+#define SEG_TYPE_MASK           0x0f
+#   define SEG_DATA_A_BIT       0x1
+#   define SEG_DATA_W_BIT       0x2
+#   define SEG_DATA_E_BIT       0x4
+#   define SEG_CODE_A_BIT       0x1
+#   define SEG_CODE_R_BIT       0x2
+#   define SEG_CODE_C_BIT       0x4
+#       define SEG_DATA_RO      0x0
+#       define SEG_DATA_ROA     0x1
+#       define SEG_DATA_RW      0x2
+#       define SEG_DATA_RWA     0x3
+#       define SEG_DATA_RO_XD   0x4
+#       define SEG_DATA_RO_XDA  0x5
+#       define SEG_DATA_RW_XW   0x6
+#       define SEG_DATA_RW_XWA  0x7
+#       define SEG_CODE_XO      0x8
+#       define SEG_CODE_XOA     0x9
+#       define SEG_CODE_XR      0xa
+#       define SEG_CODE_XRA     0xb
+#       define SEG_CODE_XO_C    0xc
+#       define SEG_CODE_XO_CA   0xd
+#       define SEG_CODE_XR_C    0xe
+#       define SEG_CODE_XR_CA   0xf
+
+/*
+** Byte 6:    sizes
+**    7:    granularity
+**    6:    d/b
+**    5:    long mode
+**    4:    available!
+**    3-0:  upper 4 bits of limit
+**    7:    base address 31:24
+*/
+#define SEG_SIZE_G_MASK         0x80
+#   define SEG_GRAN_BYTE        0x00
+#   define SEG_GRAN_4KBYTE      0x80
+
+#define SEG_SIZE_D_B_MASK       0x40
+#   define SEG_DB_16BIT         0x00
+#   define SEG_DB_32BIT         0x40
+
+#define SEG_SIZE_L_MASK         0x20
+#   define SEG_L_64BIT          0x20
+#   define SEG_L_32BIT          0x00
+
+#define SEG_SIZE_AVL_MASK       0x10
+
+#define SEG_SIZE_LIM_19_16_MASK 0x0f
+
+
+/*
+** System-segment and gate-descriptor types
+**
+** IA-32 V3, page 3-15.
+*/
+	// type 0: reserved
+#define SEG_SYS_16BIT_TSS_AVAIL 0x1
+#define SEG_SYS_LDT             0x2
+#define SEG_SYS_16BIT_TSS_BUSY  0x3
+#define SEG_SYS_16BIT_CALL_GATE 0x4
+#define SEG_SYS_TASK_GATE       0x5
+#define SEG_SYS_16BIT_INT_GATE  0x6
+#define SEG_SYS_16BIT_TRAP_GATE 0x7
+	// type 8: reserved
+#define SEG_SYS_32BIT_TSS_AVAIL 0x9
+	// type A: reserved
+#define SEG_SYS_32BIT_TSS_BUSY  0xb
+#define SEG_SYS_32BIT_CALL_GATE 0xc
+	// type D: reserved
+#define SEG_SYS_32BIT_INT_GATE  0xe
+#define SEG_SYS_32BIT_TRAP_GATE 0xf
+
+/*
+** IDT Descriptors
+** 
+** IA-32 V3, page 5-13.
+**
+** All have a segment selector in bytes 2 and 3; Task Gate descriptors
+** have bytes 0, 1, 4, 6, and 7 reserved; others have bytes 0, 1, 6,
+** and 7 devoted to the 16 bits of the Offset, with the low nybble of
+** byte 4 reserved.
+*/
+#define IDT_PRESENT             0x8000
+#define IDT_DPL_MASK            0x6000
+#   define IDT_DPL_0            0x0000
+#   define IDT_DPL_1            0x2000
+#   define IDT_DPL_2            0x4000
+#   define IDT_DPL_3            0x6000
+#define IDT_GATE_TYPE           0x0f00
+#   define IDT_TASK_GATE        0x0500
+#   define IDT_INT16_GATE       0x0600
+#   define IDT_INT32_GATE       0x0e00
+#   define IDT_TRAP16_GATE      0x0700
+#   define IDT_TRAP32_GATE      0x0f00
+
+/*
+** Interrupt vectors
+*/
+
+// predefined by the architecture
+#define VEC_DIVIDE_ERROR            0x00
+#define VEC_DEBUG_EXCEPTION         0x01
+#define VEC_NMI_INTERRUPT           0x02
+#define VEC_BREAKPOINT              0x03
+#define VEC_OVERFLOW                0x04
+#define VEC_BOUND_RANGE_EXCEEDED    0x05
+#define VEC_INVALID_OPCODE          0x06
+#define VEC_DEVICE_NOT_AVAILABLE    0x07
+#define VEC_DOUBLE_FAULT            0x08
+#define VEC_COPROCESSOR_OVERRUN     0x09
+#define VEC_INVALID_TSS             0x0a
+#define VEC_SEGMENT_NOT_PRESENT     0x0b
+#define VEC_STACK_FAULT             0x0c
+#define VEC_GENERAL_PROTECTION      0x0d
+#define VEC_PAGE_FAULT              0x0e
+// 0x0f is reserved - unused
+#define VEC_FPU_ERROR               0x10
+#define VEC_ALIGNMENT_CHECK         0x11
+#define VEC_MACHINE_CHECK           0x12
+#define VEC_SIMD_FP_EXCEPTION       0x13
+#define VEC_VIRT_EXCEPTION          0x14
+#define VEC_CTRL_PROT_EXCEPTION     0x15
+// 0x16 through 0x1f are reserved
+
+// 0x20 through 0xff are user-defined, non-reserved
+
+// IRQ0 through IRQ15 will use vectors 0x20 through 0x2f
+#define VEC_TIMER                   0x20
+#define VEC_KBD                     0x21
+#define VEC_COM2                    0x23
+#define VEC_COM1                    0x24
+#define VEC_PARALLEL                0x25
+#define VEC_FLOPPY                  0x26
+#define VEC_MYSTERY                 0x27
+#define VEC_MOUSE                   0x2c
+
+#endif
diff --git a/include/x86/bios.h b/include/x86/bios.h
new file mode 100644
index 0000000..a19e570
--- /dev/null
+++ b/include/x86/bios.h
@@ -0,0 +1,73 @@
+/*
+** @file	bios.h
+**
+** @author	Warren R. Carithers
+**
+** BIOS-related declarations
+*/
+
+#ifndef BIOS_H_
+#define BIOS_H_
+
+/*
+** BIOS-related memory addresses
+*/
+
+#define BIOS_BDA       0x0400
+
+/*
+** Selected BIOS interrupt numbers
+*/
+
+#define BIOS_TIMER     0x08
+#define BIOS_KBD       0x09
+#define BIOS_VIDEO     0x10
+#define BIOS_EQUIP     0x11
+#define BIOS_MSIZ      0x12
+#define BIOS_DISK      0x13
+#define BIOS_SERIAL    0x14
+#define BIOS_MISC      0x15
+#define BIOS_KBDSVC    0x16
+#define BIOS_PRTSVC    0x17
+#define BIOS_BOOT      0x19
+#define BIOS_RTCPCI    0x1a
+
+// BIOS video commands (AH)
+#define BV_W_ADV     0x0e
+
+// BIOS disk commands (AH)
+#define BD_RESET     0x00
+#define BD_CHECK     0x01
+#define BD_RDSECT    0x02
+#define BD_WRSECT    0x03
+#define BD_PARAMS    0x08
+
+// BIOS disk commands with parameters (AX)
+#define BD_READ(n)   ((BD_RDSECT << 8) | (n))
+#define BD_READ1     0x0201
+
+// CMOS ports (used for masking NMIs)
+#define	CMOS_ADDR    0x70
+#define	CMOS_DATA    0x71
+
+// important related commands
+#define NMI_ENABLE   0x00
+#define NMI_DISABLE  0x80
+
+/*
+** Physical Memory Map Table (0000:2D00 - 0000:7c00)
+**
+** Primarily used with the BIOS_MISC interrupt
+*/
+#define MMAP_SEG       0x02D0
+#define MMAP_DISP      0x0000
+#define MMAP_ADDR      ((MMAP_SEG << 4) + MMAP_DISP)
+#define MMAP_SECTORS   0x0a
+
+#define MMAP_ENT       24            /* bytes per entry */
+#define MMAP_MAX_ENTS  (BOOT_ADDR - MMAP_ADDR - 4) / 24
+
+#define MMAP_CODE      0xE820        /* int 0x15 code */
+#define MMAP_MAGIC_NUM 0x534D4150    /* for 0xE820 interrupt */
+
+#endif
diff --git a/include/x86/ops.h b/include/x86/ops.h
new file mode 100644
index 0000000..ad795b9
--- /dev/null
+++ b/include/x86/ops.h
@@ -0,0 +1,443 @@
+/**
+** @file	ops.h
+**
+** @author	Warren R. Carithers
+**
+** @brief	Inline escapes to assembly for efficiency
+**
+** Inspiration from:
+**	Martins Mozeiko, https://gist.github.com/mmozeiko/f68ad2546bd6ab953315
+**  MIT's xv6,       https://github.com/mit-pdos/xv6-public
+**
+** Note: normally, GCC doesn't inline unless the optimization level is
+** over 1. This can be forced by adding 
+**
+**      __attribute__((always_inline))
+**
+** after the parameter list on each declaration. This is enabled by
+** defining the compile-time CPP symbol FORCE_INLINING.
+*/
+
+#ifndef OPS_H_
+#define OPS_H_
+
+#include <common.h>
+
+#ifndef ASM_SRC
+
+// control "forced" inlining
+#ifdef FORCE_INLINING
+#define OPSINLINED    __attribute__((always_inline))
+#else
+#define OPSINLINED    /* no-op */
+#endif  /* FORCE_INLINING */
+
+/****************************
+** Data movement
+****************************/
+
+/**
+** Block move functions
+**
+** Variations:  movsb(), movsl(), movsq()
+**
+** Description:  Copy from source buffer to destination buffer
+**
+** @param dst  Destination buffer
+** @param src  Source buffer
+** @param len  Byte count
+*/
+static inline void
+movsb( void* dst, const void* src, uint32_t len ) OPSINLINED
+{
+	__asm__ __volatile__( "cld; rep movsb"
+			: "+D"(dst), "+S"(src), "+c"(len)
+			: : "memory" );
+}
+
+static inline void
+movsw( void* dst, const void* src, uint32_t len ) OPSINLINED
+{
+	__asm__ __volatile__( "cld; rep movsw"
+			: "+D"(dst), "+S"(src), "+c"(len)
+			: : "memory" );
+}
+
+static inline void
+movsl( void* dst, const void* src, uint32_t len ) OPSINLINED
+{
+	__asm__ __volatile__( "cld; rep movsl"
+			: "+D"(dst), "+S"(src), "+c"(len)
+			: : "memory" );
+}
+
+static inline void
+movsq( void* dst, const void* src, uint32_t len ) OPSINLINED
+{
+	__asm__ __volatile__( "cld; rep movsq"
+			: "+D"(dst), "+S"(src), "+c"(len)
+			: : "memory" );
+}
+
+/**
+** Block store functions
+**
+** Variations:  stosb(), stosw(), stosl()
+**
+** Description:  Store a specific value into destination buffer
+**
+** @param dst  Destination buffer
+** @param val  Data to copy
+** @param len  Byte count
+*/
+static inline void
+stosb( void *dst, uint8_t val, uint32_t len ) OPSINLINED
+{
+	__asm__ __volatile__( "cld; rep stosb"
+			: "=D" (dst), "=c" (len)
+			: "0" (dst), "1" (len), "a" (val)
+			: "memory", "cc" );
+}
+
+static inline void
+stosw( void *dst, uint16_t val, uint32_t len ) OPSINLINED
+{
+	__asm__ __volatile__( "cld; rep stos2"
+			: "=D" (dst), "=c" (len)
+			: "0" (dst), "1" (len), "a" (val)
+			: "memory", "cc" );
+}
+
+static inline void
+stosl( void *dst, uint32_t val, uint32_t len ) OPSINLINED
+{
+	__asm__ __volatile__( "cld; rep stosl"
+			: "=D" (dst), "=c" (len)
+			: "0" (dst), "1" (len), "a" (val)
+			: "memory", "cc" );
+}
+
+/****************************
+** Special register access
+****************************/
+
+/**
+** Register read functions
+**
+** Variations:  r_cr0(), r_cr2(), r_cr3(), r_cr4(), r_eflags(),
+**              r_ebp(), r_esp()
+**
+** Description:  Reads the register indicated by its name
+**
+** @return Contents of the register
+*/
+static inline uint32_t
+r_cr0( void ) OPSINLINED
+{
+	uint32_t val;
+	__asm__ __volatile__( "movl %%cr0,%0" : "=r" (val) );
+	return val;
+}
+
+static inline uint32_t
+r_cr2( void ) OPSINLINED
+{
+	uint32_t val;
+	__asm__ __volatile__( "movl %%cr2,%0" : "=r" (val) );
+	return val;
+}
+
+static inline uint32_t
+r_cr3( void ) OPSINLINED
+{
+	uint32_t val;
+	__asm__ __volatile__( "movl %%cr3,%0" : "=r" (val) );
+	return val;
+}
+
+static inline uint32_t
+r_cr4( void ) OPSINLINED
+{
+	uint32_t val;
+	__asm__ __volatile__( "movl %%cr4,%0" : "=r" (val) );
+	return val;
+}
+
+static inline uint32_t
+r_eflags(void) OPSINLINED
+{
+	uint32_t val;
+	__asm__ __volatile__( "pushfl; popl %0" : "=r" (val) );
+	return val;
+}
+
+static inline uint32_t
+r_ebp(void) OPSINLINED
+{
+	uint32_t val;
+	__asm__ __volatile__( "movl %%ebp,%0" : "=r" (val) );
+	return val;
+}
+
+static inline uint32_t
+r_esp(void) OPSINLINED
+{
+	uint32_t val;
+	__asm__ __volatile__( "movl %%esp,%0" : "=r" (val) );
+	return val;
+}
+
+/**
+** Register write functions
+**
+** Variations:  w_cr0(), w_cr2(), w_cr3(), w_cr4(), w_eflags()
+**
+** Description:  Writes a value into the CR indicated by its name
+*/
+static inline void
+w_cr0( uint32_t val ) OPSINLINED
+{
+	__asm__ __volatile__( "movl %0,%%cr0" : : "r" (val) );
+}
+
+static inline void
+w_cr2( uint32_t val ) OPSINLINED
+{
+	__asm__ __volatile__( "movl %0,%%cr2" : : "r" (val) );
+}
+
+static inline void
+w_cr3( uint32_t val ) OPSINLINED
+{
+	__asm__ __volatile__( "movl %0,%%cr3" : : "r" (val) );
+}
+
+static inline void
+w_cr4( uint32_t val ) OPSINLINED
+{
+	__asm__ __volatile__( "movl %0,%%cr4" : : "r" (val) );
+}
+
+static inline void
+w_eflags(uint32_t eflags) OPSINLINED
+{
+	__asm__ __volatile__( "pushl %0; popfl" : : "r" (eflags) );
+}
+
+/**
+** Descriptor table load functions
+**
+** Variations:  w_gdt(), w_idt()
+**
+** Description:  Load an address into the specified processor register
+**
+** @param addr  The value to be loaded into the register
+*/
+static inline void
+w_gdt( void *addr ) OPSINLINED
+{
+	__asm__ __volatile__( "lgdt (%0)" : : "r" (addr) );
+}
+
+static inline void
+w_idt( void *addr ) OPSINLINED
+{
+	__asm__ __volatile__( "lidt (%0)" : : "r" (addr) );
+}
+
+/**
+** CPU ID access
+**
+** Description:  Retrieve CPUID information
+**
+** @param op  Value to be placed into %eax for the operation
+** @param ap   Pointer to where %eax contents should be saved, or NULL
+** @param bp   Pointer to where %ebx contents should be saved, or NULL
+** @param cp   Pointer to where %ecx contents should be saved, or NULL
+** @param dp   Pointer to where %edx contents should be saved, or NULL
+*/
+static inline void
+cpuid( uint32_t op, uint32_t *ap, uint32_t *bp,
+		uint32_t *cp, uint32_t *dp ) OPSINLINED
+{
+	uint32_t eax, ebx, ecx, edx;
+	__asm__ __volatile__( "cpuid"
+			: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+			: "a" (op) );
+
+	if( ap ) *ap = eax;
+	if( bp ) *bp = ebx;
+	if( cp ) *cp = ecx;
+	if( dp ) *dp = edx;
+}
+
+/****************************
+** TLB management
+****************************/
+
+/**
+** TLB invalidation for one page
+**
+** Description:  Invalidate the TLB entry for an address
+**
+** @param addr  An address within the page to be flushed
+*/
+static inline void
+invlpg( uint32_t addr ) OPSINLINED
+{
+	__asm__ __volatile__( "invlpg (%0)" : : "r" (addr) : "memory" );
+}
+
+/**
+** TLB invalidation for all pages
+**
+** Description:  Flush all entries from the TLB
+**
+** We do this by changing CR3.
+*/
+static inline void
+flushtlb( void ) OPSINLINED
+{
+	uint32_t cr3;
+	__asm__ __volatile__( "movl %%cr3,%0" : "=r" (cr3) );
+	__asm__ __volatile__( "movl %0,%%cr2" : : "r" (cr3) );
+}
+
+/****************************
+** I/O instructions
+****************************/
+
+/**
+** Name:	inN
+**
+** Variations:  inb(), inw(), inl()
+**
+** Description:  Read some amount of data from the supplied I/O port
+**
+** @param port  The i/o port to read from
+**
+** @return The data read from the specified port
+*/
+static inline uint8_t
+inb( int port ) OPSINLINED
+{
+	uint8_t data;
+	__asm__ __volatile__( "inb %w1,%0" : "=a" (data) : "d" (port) );
+	return data;
+}
+
+static inline uint16_t
+inw( int port ) OPSINLINED
+{
+	uint16_t data;
+	__asm__ __volatile__( "inw %w1,%0" : "=a" (data) : "d" (port) );
+	return data;
+}
+
+static inline uint32_t
+inl( int port ) OPSINLINED
+{
+	uint32_t data;
+	__asm__ __volatile__( "inl %w1,%0" : "=a" (data) : "d" (port) );
+	return data;
+}
+
+/**
+** Name:	outN
+**
+** Variations:  outb(), outw(), outl()
+**
+** Description:  Write some data to the specified I/O port
+**
+** @param port  The i/o port to write to
+** @param data  The data to be written to the port
+**
+** @return The data read from the specified port
+*/
+static inline void
+outb( int port, uint8_t data ) OPSINLINED
+{
+	__asm__ __volatile__( "outb %0,%w1" : : "a" (data), "d" (port) );
+}
+
+static inline void
+outw( int port, uint16_t data ) OPSINLINED
+{
+	__asm__ __volatile__( "outw %0,%w1" : : "a" (data), "d" (port) );
+}
+
+static inline void
+outl( int port, uint32_t data ) OPSINLINED
+{
+	__asm__ __volatile__( "outl %0,%w1" : : "a" (data), "d" (port) );
+}
+
+/****************************
+** Miscellaneous instructions
+****************************/
+
+/**
+** Name:	breakpoint
+**
+** Description:  Cause a breakpoint interrupt for debugging purposes
+*/
+static inline void
+breakpoint( void ) OPSINLINED
+{
+	__asm__ __volatile__( "int3" );
+}
+
+/**
+** Name:	get_ra
+**
+** Description:  Get the return address for the calling function
+**              (i.e., where whoever called us will go back to)
+**
+** @return The address the calling routine will return to as a uint32_t
+*/
+static inline uint32_t
+get_ra( void ) OPSINLINED
+{
+	uint32_t val;
+	__asm__ __volatile__( "movl 4(%%ebp),%0" : "=r" (val) );
+	return val;
+}
+
+/**
+** Name:	ev_wait
+**
+** Description:  Pause until something happens
+*/
+static inline void
+ev_wait( void ) OPSINLINED
+{
+	__asm__ __volatile__( "sti ; hlt" );
+}
+
+
+/**
+** Name:	xchgl
+**
+** Description:  Perform an atomic exchange with memory
+**
+** @param addr  Memory location to be modified
+** @param data  Data to exchange
+**
+** @return The old contents of the memory location
+*/
+static inline uint32_t
+xchgl( volatile uint32_t *addr, uint32_t data ) OPSINLINED
+{
+	uint32_t old;
+
+	// + indicates a read-modify-write operand
+	__asm__ __volatile__( "lock; xchgl %0, %1"
+		     : "+m" (*addr), "=a" (old)
+		     : "1" (data)
+		     : "cc");
+	return old;
+}
+
+#endif  /* !ASM_SRC */
+
+#endif
diff --git a/include/x86/pic.h b/include/x86/pic.h
new file mode 100644
index 0000000..d4fa93b
--- /dev/null
+++ b/include/x86/pic.h
@@ -0,0 +1,139 @@
+/**
+** @file	pic.h
+**
+** @author	Warren R. Carithers
+** @author	K. Reek
+**
+** Definitions of constants and macros for the Intel 8259 Programmable
+** Interrupt Controller.
+**
+*/
+
+#ifndef X86PIC_H_
+#define X86PIC_H_
+
+/*
+** Our expected configuration is two PICs, with the secondary connected
+** through the IRQ2 pin of the primary.
+*/
+
+/*
+** Port addresses for the command port and interrupt mask register port
+** for both the primary and secondary PICs.
+*/
+#define PIC1_CMD		0x20			// primary command
+#define PIC1_DATA		(PIC1_CMD + 1)	// primary data / int mask register
+#define PIC2_CMD		0xA0			// secondary command
+#define PIC2_DATA		(PIC2_CMD + 1)	// secondary data / int mask register
+
+/*
+** Initialization Command Word (ICW) definitions
+**
+** Initialization sequence:
+**    ICW1 Init command is sent to each command port.
+**    ICW2 vector commands are sent to the data ports.
+**    If "cascade mode" was selected, send ICW3 commands to the data ports.
+**    If "need ICW4" was selected, send ICW4 commands to the data ports.
+**
+** Following that sequence, the PIC is ready to accept interrupts;
+** it will also accept Output Command Words (OCWs) to the data ports.
+**
+** PIC1_* defines are intended for the primary PIC
+** PIC2_* defines are intended for the secondary PIC
+** PIC_* defines are sent to both PICs
+*/
+
+/*
+** ICW1: initialization, send to command port
+*/
+#define PIC_CW1_INIT		0x10	// start initialization sequence
+#define PIC_CW1_NEED4		0x01	// ICW4 will also be set
+#define PIC_CW1_SINGLE		0x02	// select single (vs. cascade) mode
+#define PIC_CW1_INTVAL		0x04	// set call interval to 4 (vs. 8)
+#define PIC_CW1_LEVEL		0x08	// use level-triggered mode (vs. edge)
+
+/*
+** ICW2: interrupt vector base offsets, send to data port
+*/
+#define	PIC1_CW2_VECBASE	0x20	// IRQ0 int vector number
+#define	PIC2_CW2_VECBASE	0x28	// IRQ8 int vector number
+
+/*
+** ICW3: secondary::primary attachment, send to data port
+*/
+#define PIC1_CW3_SEC_IRQ2	0x04	// bit mask: secondary is on pin 2
+#define PIC2_CW3_SEC_ID		0x02	// integer: secondary id
+
+/*
+** ICW4: operating mode, send to data port
+*/
+#define PIC_CW4_PM86		0x01	// 8086 mode (vs. 8080/8085)
+#define PIC_CW4_AUTOEOI		0x02	// do auto eoi's
+#define	PIC_CW4_UNBUF		0x00	// unbuffered mode
+#define PIC_CW4_SEC_BUF		0x08	// put secondary in buffered mode
+#define PIC_CW4_PRI_BUF		0x0C	// put primary in buffered mode
+#define PIC_CW4_SFNMODE		0x10	// "special fully nested" mode
+
+/*
+** Operation Control Words (OCWs)
+**
+** After the init sequence, can send these
+*/
+
+/*
+** OCW1: interrupt mask; send to data port
+*/
+#define	PIC_MASK_NONE		0x00	// allow all interrupts
+#define	PIC_MASK_NO_IRQ0	0x01	// prevent IRQ0 interrupts
+#define	PIC_MASK_NO_IRQ1	0x02	// prevent IRQ1 interrupts
+#define	PIC_MASK_NO_IRQ2	0x04	// prevent IRQ2 interrupts
+#define	PIC_MASK_NO_IRQ3	0x08	// prevent IRQ3 interrupts
+#define	PIC_MASK_NO_IRQ4	0x10	// prevent IRQ4 interrupts
+#define	PIC_MASK_NO_IRQ5	0x20	// prevent IRQ5 interrupts
+#define	PIC_MASK_NO_IRQ6	0x40	// prevent IRQ6 interrupts
+#define	PIC_MASK_NO_IRQ7	0x80	// prevent IRQ7 interrupts
+#define	PIC_MASK_ALL		0xff	// prevent all interrupts
+
+/*
+** OCW2: EOI control, interrupt level; send to command port
+*/
+#define	PIC_LVL_0			0x00	// act on IRQ level 0
+#define	PIC_LVL_1			0x01	// act on IRQ level 1
+#define	PIC_LVL_2			0x02	// act on IRQ level 2
+#define	PIC_LVL_3			0x03	// act on IRQ level 3
+#define	PIC_LVL_4			0x04	// act on IRQ level 4
+#define	PIC_LVL_5			0x05	// act on IRQ level 5
+#define	PIC_LVL_6			0x06	// act on IRQ level 6
+#define	PIC_LVL_7			0x07	// act on IRQ level 7
+
+#define	PIC_EOI_NON_SPEC	0x20	// non-specific EOI command
+#	define PIC_EOI			PIC_EOI_NON_SPEC
+
+#define	PIC_EOI_SPEC		0x60	// specific EOI command
+#	define PIC_SEOI			PIC_EOI_SPEC
+#	define PIC_SEOI_LVL0	(PIC_EOI_SPEC | PIC_LVL_0)
+#	define PIC_SEOI_LVL1	(PIC_EOI_SPEC | PIC_LVL_1)
+#	define PIC_SEOI_LVL2	(PIC_EOI_SPEC | PIC_LVL_2)
+#	define PIC_SEOI_LVL3	(PIC_EOI_SPEC | PIC_LVL_3)
+#	define PIC_SEOI_LVL4	(PIC_EOI_SPEC | PIC_LVL_4)
+#	define PIC_SEOI_LVL5	(PIC_EOI_SPEC | PIC_LVL_5)
+#	define PIC_SEOI_LVL6	(PIC_EOI_SPEC | PIC_LVL_6)
+#	define PIC_SEOI_LVL7	(PIC_EOI_SPEC | PIC_LVL_7)
+
+#define	PIC_EOI_ROT_NONSP		0xa0	// rotate on non-spec EOI cmd
+#define	PIC_EOI_SET_ROT_AUTO	0x80	// set "rotate in auto EOI mode"
+#define	PIC_EOI_CLR_ROT_AUTO	0x00	// clear "rotate in auto EOI mode"
+#define	PIC_EOI_ROT_SPEC		0xe0	// rotate on spec EOI cmd (+ level)
+#define	PIC_EOI_SET_PRIO		0xc0	// set priority (+ level)
+#define	PIC_EOI_NOP				0x40	// no operation
+
+/*
+** OCW3: read requests, special mask mode; send to command port 
+*/
+#define PIC_READIRR			0x0a	// read the IR register
+#define PIC_READISR			0x0b	// read the IS register
+#define	PIC_POLL			0x0c	// poll
+#define	PIC_MASK_RESET		0x48	// reset special mask mode
+#define	PIC_MASK_SET		0x68	// set special mask mode
+
+#endif
diff --git a/include/x86/pit.h b/include/x86/pit.h
new file mode 100644
index 0000000..269fcec
--- /dev/null
+++ b/include/x86/pit.h
@@ -0,0 +1,82 @@
+/*
+** @file    pit.h
+**
+** @author  Warren R. Carithers
+** @author	K. Reek
+**
+** Definitions of constants and macros for the
+** Intel 8254 Programmable Interval Timer
+**
+*/
+
+#ifndef X86PIT_H_
+#define X86PIT_H_
+
+
+/*
+** Hardware timer (Intel 8254 Programmable Interval Timer)
+**
+** Control word layout:
+**
+**   Bit     7   6 | 5   4 | 3   2   1 | 0
+**   Field  SC1 SC0|RW1 RW0|M2  M1  M0 |BCD
+**
+** SC  - select counter
+** RW  - read/write
+** M   - mode
+** BCD - binary or BCD counter
+*/
+
+/* Frequency settings */
+#define	PIT_DEFAULT_TICKS_PER_SECOND	18		// actually 18.2065Hz
+#define	PIT_DEFAULT_MS_PER_TICK			(1000/PIT_DEFAULT_TICKS_PER_SECOND)
+#define	PIT_FREQ						1193182	// clock cycles/sec
+
+/* Port assignments */
+#define	PIT_BASE_PORT		0x40	// I/O port for the timer
+#	define	PIT_0_PORT			(PIT_BASE_PORT)
+#	define	PIT_1_PORT			(PIT_BASE_PORT+1)
+#	define	PIT_2_PORT			(PIT_BASE_PORT+2)
+#	define	PIT_CONTROL_PORT	(PIT_BASE_PORT+3)
+
+/* BCD field */
+#define	PIT_USE_DECIMAL		0x00	// 16-bit binary counter (default)
+#define	PIT_USE_BCD			0x01	// BCD counter
+
+/* Timer modes */
+#define	PIT_MODE_0			0x00	// int on terminal count
+#define	PIT_MODE_1			0x02	// one-shot
+#define	PIT_MODE_2			0x04	// divide-by-N
+#define	PIT_MODE_3			0x06	// square-wave
+#define	PIT_MODE_4			0x08	// software strobe
+#define	PIT_MODE_5			0x0a	// hardware strobe
+
+/* Timer 0 settings */
+#define	PIT_0_SELECT		0x00		// select timer 0
+#define	PIT_0_LOAD			0x30		// load LSB, then MSB
+#define	PIT_0_NDIV			PIT_MODE_2	// divide-by-N counter
+#define	PIT_0_SQUARE		PIT_MODE_3	// square-wave mode
+#define	PIT_0_ENDSIGNAL		0x00		// assert OUT at end of count
+
+/* Timer 1 settings */
+#define	PIT_1_SELECT		0x40	// select timer 1
+#define	PIT_1_READ			0x30	// read/load LSB then MSB
+#define	PIT_1_RATE			0x06	// square-wave, for USART
+
+/* Timer 2 settings */
+#define	PIT_2_SELECT		0x80	// select timer 1
+#define	PIT_2_READ			0x30	// read/load LSB then MSB
+#define	PIT_2_RATE			0x06	// square-wave, for USART
+
+/* Timer read-back */
+#define	PIT_READBACK		0xc0	// perform a read-back
+#define	PIT_RB_NOT_COUNT	0x20	// don't latch the count
+#define	PIT_RB_NOT_STATUS	0x10	// don't latch the status
+#define	PIT_RB_CHAN_2		0x08	// read back channel 2
+#define	PIT_RB_CHAN_1		0x04	// read back channel 1
+#define	PIT_RB_CHAN_0		0x02	// read back channel 0
+#define	PIT_RB_ACCESS_MASK	0x30	// access mode field
+#define	PIT_RB_OP_MASK		0x0e	// oper mode field
+#define	PIT_RB_BCD_MASK		0x01	// BCD mode field
+
+#endif
diff --git a/include/x86/uart.h b/include/x86/uart.h
new file mode 100644
index 0000000..0c6194b
--- /dev/null
+++ b/include/x86/uart.h
@@ -0,0 +1,349 @@
+/*
+** @file	uart.h
+**
+** @author	M. Reek
+** @authors	K. Reek, Warren R. Carithers
+**
+** Definitions for a 16540/16550 compatible UART.  Definitions are taken
+** from datasheets for the National Semiconductor INS8250, NS16450, and
+** NS16550 UART chips, and the PC87309 Super I/O legacy peripheral chip.
+**
+** The naming convention is UAx_yyy_zzzzz.  "x" is either 4 or 5 (see below),
+** "yyy" is the name of the register to which this value applies, and
+** "zzzzz" is the name of the value or field.
+**
+** The UA4 prefix denotes 16540 compatible functions, available in both
+** chips. The UA5 prefix denotes 16550-only functions (primarily the FIFOs).
+**
+** For many items there are two names: one short one that matches the name
+** in the chip manual, and another that is more readable.
+*/
+
+#ifndef UART_H
+#define	UART_H
+
+/*********************************************************************
+***************************** I/O PORTS ******************************
+*********************************************************************/
+
+/*
+** Base port number assigned to the device
+*/
+#define	UA4_COM1_PORT	0x3f8
+#define	UA4_COM2_PORT	0x2f8
+#define	UA4_COM3_PORT	0x3e8
+#define	UA4_COM4_PORT	0x2e8
+
+// short name for the one we'll use
+#define	UA4_PORT		UA4_COM1_PORT
+#define UA5_PORT		UA4_COM1_PORT
+
+/*
+** Registers
+**
+** The 164x0 chips have the following registers. The (RO) and (WO)
+** suffixes indicate read-only and write-only access.
+**
+**   Index  Register(s)
+**   =====  =========================================
+**     0    Receiver Data (RO), Transmitter Data (WO)
+**     1    Interrupt Enable 
+**     2    Interrupt ID (RO), FIFO Control (WO)
+**     3    Line Control, Divisor Latch
+**     4    Modem Control
+**     5    Line Status
+**     6    Modem Status
+**     7    Scratch
+**
+** Registers indices are relative to the base I/O port for the
+** specific UART port being used (e.g., for COM1, the port addresses
+** are 0x3f8 through 0x3ff). When two registers share a port and have
+** different access methods (RO vs. WO), a read from the port accesses
+** the RO register and a write to the port access the WO register.
+**
+** The Line Control and Divisor Latch registers are accessed by writing
+** a byte to the port; the high-order bit determines which register is
+** accessed (0 selects Line Control, 1 selects Divisor Latch), with the
+** remaining bits selecting fields within the indicated register.
+*/
+
+/*
+** Receiver Data Register (read-only)
+*/
+#define	UA4_RXD				(UA4_PORT+0)
+#	define	UA4_RX_DATA			UA4_RXD
+
+/*
+** Transmitter Data Register (write-only)
+*/
+#define	UA4_TXD				(UA4_PORT+0)
+#	define	UA4_TX_DATA			UA4_TXD
+
+/*
+** Interrupt Enable Register
+*/
+#define	UA4_IER				(UA4_PORT+1)
+#	define	UA4_INT_ENABLE_REG	UA4_IER
+
+// fields
+#define	UA4_IER_RX_IE		0x01	// Rcvr High-Data-Level Int Enable
+#define	UA4_IER_TX_IE		0x02	// Xmitter Low-data-level Int Enable
+#define	UA4_IER_LS_IE		0x04	// Line Status Int Enable
+#define	UA4_IER_MS_IE		0x08	// Modem Status Int Enable
+
+// aliases
+#define	UA4_IER_RX_INT_ENABLE			UA4_IER_RX_IE
+#define	UA4_IER_TX_INT_ENABLE			UA4_IER_TX_IE
+#define	UA4_IER_LINE_STATUS_INT_ENABLE	UA4_IER_LS_IE
+#define	UA4_IER_MODEM_STATUS_INT_ENABLE	UA4_IER_MS_IE
+
+/*
+** Interrupt Identification Register (read-only)
+**
+** a.k.a. Event Identification Register
+*/
+#define	UA4_IIR				(UA4_PORT+2)
+#	define	UA4_EVENT_ID		UA4_IIR
+
+// fields
+#define	UA4_IIR_IPF			0x01	// Interrupt Pending flag
+
+#define	UA4_IIR_IPR_MASK	0x06	// Interrupt Priority mask
+#	define	UA4_IIR_IPR0_MASK	0x02	// IPR bit 0 mask
+#	define	UA4_IIR_IPR1_MASK	0x04	// IPR bit 1 mask
+
+#define	UA5_IIR_RXFT		0x08	// RX_FIFO Timeout
+#define	UA5_IIR_FEN0		0x40	// FIFOs Enabled
+#define	UA5_IIR_FEN1		0x80	// FIFOs Enabled
+
+// aliases
+#define	UA4_IIR_INT_PENDING		UA4_IIR_IPF
+#define	UA4_IIR_INT_PRIORITY	UA4_IIR_IPR
+#define	UA5_IIR_RX_FIFO_TIMEOUT	UA5_IIR_RXFT
+#define	UA5_IIR_FIFO_ENABLED_0	UA5_IIR_FEN0
+#define	UA5_IIR_FIFO_ENABLED_1	UA5_IIR_FEN1
+
+// IIR interrupt priorities (four-bit values)
+#define	UA4_IIR_INT_PRI_MASK	0x0f	// Mask for extracting int priority
+#	define	UA4_IIR_NO_INT			0x01	// no interrupt
+#	define	UA4_IIR_LINE_STATUS		0x06	// line status interrupt
+#	define	UA4_IIR_RX				0x04	// Receiver High Data Level
+#	define	UA5_IIR_RX_FIFO			0x0c	// Receiver FIFO timeout (16550)
+#	define	UA4_IIR_TX				0x02	// Transmitter Low Data level
+#	define	UA4_IIR_MODEM_STATUS	0x00	// Modem Status
+
+// aliases
+#define	UA4_IIR_NO_INT_PENDING				UA4_IIR_NO_INT
+#define	UA4_IIR_LINE_STATUS_INT_PENDING		UA4_IIR_LINE_STATUS
+#define	UA4_IIR_RX_INT_PENDING				UA4_IIR_RX
+#define	UA5_IIR_RX_FIFO_TIMEOUT_INT_PENDING	UA5_IIR_RX_FIFO
+#define	UA4_IIR_TX_INT_PENDING				UA4_IIR_TX
+#define	UA4_IIR_MODEM_STATUS_INT_PENDING	UA4_IIR_MODEM_STATUS
+
+/*
+** FIFO Control Register (16550 only, write-only)
+*/
+#define	UA5_FCR				(UA5_PORT+2)
+#	define	UA5_FIFO_CTL		UA5_FCR
+
+#define	UA5_FCR_FIFO_RESET	0x00	// Reset the FIFO
+#define	UA5_FCR_FIFO_EN		0x01	// FIFO Enable
+#define	UA5_FCR_RXSR		0x02	// Receiver Soft Reset
+#define	UA5_FCR_TXSR		0x04	// Transmitter Soft Reset
+
+#define	UA5_FCR_TXFT_MASK	0x30	// TX_FIFO threshold level mask
+#	define	UA5_FCR_TXFT0_MASK	0x10	// TXFT bit 0 mask
+#	define	UA5_FCR_TXFT1_MASK	0x20	// TXFT bit 1 mask
+#		define	UA5_FCR_TX_FIFO_1	0x00	// 1 char
+#		define	UA5_FCR_TX_FIFO_3	0x10	// 3 char
+#		define	UA5_FCR_TX_FIFO_9	0x20	// 9 char
+#		define	UA5_FCR_TX_FIFO_13	0x30	// 13 char
+
+#define	UA5_FCR_RXFT_MASK	0xc0	// RX_FIFO threshold level mask
+#	define	UA5_FCR_RXFT0_MASK	0x40	// RXFT bit 0 mask
+#	define	UA5_FCR_RXFT1_MASK	0x80	// RXFT bit 1 mask
+#		define	UA5_FCR_RX_FIFO_1	0x00	// 1 char
+#		define	UA5_FCR_RX_FIFO_4	0x40	// 4 char
+#		define	UA5_FCR_RX_FIFO_8	0x80	// 8 char
+#		define	UA5_FCR_RX_FIFO_14	0xc0	// 14 char
+
+// aliases
+#define	UA5_FCR_FIFO_ENABLED	UA5_FCR_FIFO_EN
+#define	UA5_FCR_RX_SOFT_RESET	UA5_FCR_RXSR
+#define	UA5_FCR_TX_SOFT_RESET	UA5_FCR_TXSR
+#define	UA5_FCR_TX_FIFO_1_CHAR	UA5_FCR_TX_FIFO_1
+#define	UA5_FCR_TX_FIFO_3_CHAR	UA5_FCR_TX_FIFO_3
+#define	UA5_FCR_TX_FIFO_9_CHAR	UA5_FCR_TX_FIFO_9
+#define	UA5_FCR_TX_FIFO_13_CHAR	UA5_FCR_TX_FIFO_13
+#define	UA5_FCR_RX_FIFO_1_CHAR	UA5_FCR_RX_FIFO_1
+#define	UA5_FCR_RX_FIFO_4_CHAR	UA5_FCR_RX_FIFO_4
+#define	UA5_FCR_RX_FIFO_8_CHAR	UA5_FCR_RX_FIFO_8
+#define	UA5_FCR_RX_FIFO_14_CHAR	UA5_FCR_RX_FIFO_14
+
+/*
+** Line Control Register (available in all banks)
+**
+** Selected when bit 7 of the value written to the port is a 0.
+*/
+#define	UA4_LCR				(UA4_PORT+3)
+#	define	UA4_LINE_CTL		UA4_LCR
+
+#define	UA4_LCR_WLS_MASK	0x03	// Word Length Select mask
+#	define	UA4_LCR_WLS0_MASK	0x01	// WLS bit 0 mask
+#	define	UA4_LCR_WLS1_MASK	0x02	// WLS bit 1 mask
+#		define	UA4_LCR_WLS_5		0x00	// 5 bits per char
+#		define	UA4_LCR_WLS_6		0x01	// 6 bits per char
+#		define	UA4_LCR_WLS_7		0x02	// 7 bits per char
+#		define	UA4_LCR_WLS_8		0x03	// 8 bits per char
+
+#define	UA4_LCR_STB			0x04	// Stop Bits
+#		define	UA4_LCR_1_STOP_BIT	0x00
+#		define	UA4_LCR_2_STOP_BIT	0x04
+
+#define	UA4_LCR_PEN			0x08	// Parity Enable
+#define	UA4_LCR_EPS			0x10	// Even Parity Select
+#define	UA4_LCR_STKP		0x20	// Sticky Parity
+#		define	UA4_LCR_NO_PARITY		0x00
+#		define	UA4_LCR_ODD_PARITY		UA4_LCR_PEN
+#		define	UA4_LCR_EVEN_PARITY		(UA4_LCR_PEN|UA4_LCR_EPS)
+#		define	UA4_LCR_PARITY_LOGIC_1	(UA4_LCR_PEN|UA4_LCR_STKP)
+#		define	UA4_LCR_PARITY_LOGIC_0	(UA4_LCR_PEN|UA4_LCR_EPS|UA4_LCR_STKP)
+
+#define	UA4_LCR_SBRK		0x40	// Set Break
+#define	UA4_LCR_DLAB		0x80	// Divisor Latch select bit
+
+// aliases
+#	define	UA4_LCR_STOP_BITS		UA4_LCR_STB
+#	define	UA4_LCR_PARITY_ENABLE	UA4_LCR_PEN
+#	define	UA4_LCR_SET_BREAK		UA4_LCR_SBRK
+#	define	UA4_LCR_BANK_SELECT_ENABLE	UA4_LCR_BKSE
+
+/*
+** Divisor Latch Registers
+**     Divisor Latch Least Significant (DLL)
+**     Divisor Latch Most Significant (DLM)
+**
+** These contain the lower and upper halves of the 16-bit divisor for
+** baud rate generation.
+**
+** Accessing them requires sending a command to LCR with the most
+** significant bit (0x80, the DLAB field) set. This "unlocks" the
+** Divisor Latch registers, which are accessed at UA4_PORT+0 and
+** UA4_PORT+1 (i.e., in place of the RXD/TXD and IE registers). To
+** "re-lock" the Divisor Latch registers, write a command byte to
+** LCR with 0 in the DLAB bit.
+*/
+#define	UA4_DLL				(UA4_PORT+0)	// Divisor Latch (least sig.)
+#define	UA4_DLM				(UA4_PORT+1)	// Divisor Latch (most sig.)
+
+// aliases
+#define	UA4_DIVISOR_LATCH_LS	UA4_DLL
+#define	UA4_DIVISOR_LATCH_MS	UA4_DLM
+
+// Baud rate divisor high and low bytes
+#define	BAUD_HIGH_BYTE(x)	(((x) >> 8) & 0xff)
+#define	BAUD_LOW_BYTE(x)	((x) & 0xff)
+
+// Baud rate divisors
+#define	DL_BAUD_50			2304
+#define	DL_BAUD_75			1536
+#define	DL_BAUD_110			1047
+#define	DL_BAUD_150			768
+#define	DL_BAUD_300			384
+#define	DL_BAUD_600			192
+#define	DL_BAUD_1200		96
+#define	DL_BAUD_1800		64
+#define	DL_BAUD_2000		58
+#define	DL_BAUD_2400		48
+#define	DL_BAUD_3600		32
+#define	DL_BAUD_4800		24
+#define	DL_BAUD_7200		16
+#define	DL_BAUD_9600		12
+#define	DL_BAUD_14400		8
+#define	DL_BAUD_19200		6
+#define	DL_BAUD_28800		4
+#define	DL_BAUD_38400		3
+#define	DL_BAUD_57600		2
+#define	DL_BAUD_115200		1
+
+/*
+** Modem Control Register
+*/
+#define	UA4_MCR				(UA4_PORT+4)
+#	define	UA4_MODEM_CTL		UA4_MCR
+
+#define	UA4_MCR_DTR			0x01	// Data Terminal Ready
+#define	UA4_MCR_RTS			0x02	// Ready to Send
+#define	UA4_MCR_RILP		0x04	// Loopback Interrupt Request
+#define	UA4_MCR_ISEN		0x08	// Interrupt Signal Enable
+#define	UA4_MCR_DCDLP		0x08	// DCD Loopback
+#define	UA4_MCR_LOOP		0x10	// Loopback Enable
+
+// aliases
+#define	UA4_MCR_DATA_TERMINAL_READY		UA4_MCR_DTR
+#define	UA4_MCR_READY_TO_SEND			UA4_MCR_RTS
+#define	UA4_MCR_LOOPBACK_INT_REQ		UA4_MCR_RILP
+#define	UA4_MCR_INT_SIGNAL_ENABLE		UA4_MCR_ISEN
+#define	UA4_MCR_LOOPBACK_DCD			UA4_MCR_DCDLP
+#define	UA4_MCR_LOOPBACK_ENABLE			UA4_MCR_LOOP
+
+/*
+** Line Status Register
+*/
+#define	UA4_LSR				(UA4_PORT+5)
+#	define	UA4_LINE_STATUS		UA4_LSR
+
+#define	UA4_LSR_RXDA		0x01	// Receiver Data Available
+#define	UA4_LSR_OE			0x02	// Overrun Error
+#define	UA4_LSR_PE			0x04	// Parity Error
+#define	UA4_LSR_FE			0x08	// Framing Error
+#define	UA4_LSR_BRK			0x10	// Break Event Detected
+#define	UA4_LSR_TXRDY		0x20	// Transmitter Ready
+#define	UA4_LSR_TXEMP		0x40	// Transmitter Empty
+#define	UA4_LSR_ER_INF		0x80	// Error in RX_FIFO
+
+// aliases
+#define	UA4_LSR_RX_DATA_AVAILABLE	UA4_LSR_RXDA
+#define	UA4_LSR_OVERRUN_ERROR		UA4_LSR_OE
+#define	UA4_LSR_PARITY_ERROR		UA4_LSR_PE
+#define	UA4_LSR_FRAMING_ERROR		UA4_LSR_FE
+#define	UA4_LSR_BREAK_DETECTED		UA4_LSR_BRK
+#define	UA4_LSR_TX_READY			UA4_LSR_TXRDY
+#define	UA4_LSR_TX_EMPTY			UA4_LSR_TXEMP
+#define	UA4_LSR_RX_FIFO_ERROR		UA4_LSR_ER_INF
+
+/*
+** Modem Status Register
+*/
+#define	UA4_MSR				(UA4_PORT+6)
+#	define	UA4_MODEM_STATUS	UA4_MSR
+
+#define	UA4_MSR_DCTS		0x01	// Delta Clear to Send
+#define	UA4_MSR_DDSR		0x02	// Delta Data Set Ready
+#define	UA4_MSR_TERI		0x04	// Trailing Edge Ring Indicate
+#define	UA4_MSR_DDCD		0x08	// Delta Data Carrier Detect
+#define	UA4_MSR_CTS			0x10	// Clear to Send
+#define	UA4_MSR_DSR			0x20	// Data Set Ready
+#define	UA4_MSR_RI			0x40	// Ring Indicate
+#define	UA4_MSR_DCD			0x80	// Data Carrier Detect
+
+// aliases
+#define	UA4_MSR_DELTA_CLEAR_TO_SEND			UA4_MSR_DCTS
+#define	UA4_MSR_DELTA_DATA_SET_READY		UA4_MSR_DDSR
+#define	UA4_MSR_TRAILING_EDGE_RING			UA4_MSR_TERI
+#define	UA4_MSR_DELTA_DATA_CARRIER_DETECT	UA4_MSR_DDCD
+#define	UA4_MSR_CLEAR_TO_SEND				UA4_MSR_CTS
+#define	UA4_MSR_DATA_SET_READY				UA4_MSR_DSR
+#define	UA4_MSR_RING_INDICATE				UA4_MSR_RI
+#define	UA4_MSR_DATA_CARRIER_DETECT			UA4_MSR_DCD
+
+/*
+** Scratch Register
+**
+** Not used by the UART; usable as a "scratchpad" register for
+** temporary storage.
+*/
+#define	UA4_SCR				(UA4_PORT+7)
+#	define	UA4_SCRATCH			UA4_UA5_SCR
+
+#endif	/* uart.h */