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//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-23083092
// Cuda compilation tools, release 9.1, V9.1.85
// Based on LLVM 3.4svn
//
.version 6.1
.target sm_30
.address_size 64
// .globl __raygen__oxMain
.const .align 8 .b8 cs[32];
.visible .entry __raygen__oxMain(
)
{
.reg .pred %p<3>;
.reg .b16 %rs<12>;
.reg .f32 %f<26>;
.reg .b32 %r<9>;
.reg .b64 %rd<13>;
// inline asm
call (%r1), _optix_get_launch_index_x, ();
// inline asm
// inline asm
call (%r2), _optix_get_launch_index_y, ();
// inline asm
ld.const.u64 %rd3, [cs+8];
cvta.to.global.u64 %rd4, %rd3;
ld.const.v2.u32 {%r4, %r5}, [cs+24];
mad.lo.s32 %r7, %r4, %r2, %r1;
cvt.u64.u32 %rd1, %r7;
mul.wide.u32 %rd5, %r7, 16;
add.s64 %rd6, %rd4, %rd5;
ld.global.v4.f32 {%f10, %f24, %f12, %f13}, [%rd6];
setp.eq.s32 %p1, %r5, 1;
selp.f32 %f23, %f12, %f10, %p1;
selp.f32 %f25, %f10, %f12, %p1;
setp.eq.s32 %p2, %r5, 0;
ld.const.u64 %rd2, [cs];
@%p2 bra BB0_2;
cvta.to.global.u64 %rd7, %rd2;
shl.b64 %rd8, %rd1, 3;
add.s64 %rd9, %rd7, %rd8;
ld.global.v4.u16 {%rs4, %rs5, %rs6, %rs7}, [%rd9];
// inline asm
{ cvt.f32.f16 %f16, %rs4;}
// inline asm
// inline asm
{ cvt.f32.f16 %f17, %rs5;}
// inline asm
// inline asm
{ cvt.f32.f16 %f18, %rs6;}
// inline asm
min.f32 %f23, %f23, %f16;
min.f32 %f24, %f24, %f17;
min.f32 %f25, %f25, %f18;
BB0_2:
cvta.to.global.u64 %rd10, %rd2;
shl.b64 %rd11, %rd1, 3;
add.s64 %rd12, %rd10, %rd11;
mov.f32 %f22, 0f3F800000;
// inline asm
{ cvt.rn.f16.f32 %rs11, %f22;}
// inline asm
// inline asm
{ cvt.rn.f16.f32 %rs10, %f25;}
// inline asm
// inline asm
{ cvt.rn.f16.f32 %rs9, %f24;}
// inline asm
// inline asm
{ cvt.rn.f16.f32 %rs8, %f23;}
// inline asm
st.global.v4.u16 [%rd12], {%rs8, %rs9, %rs10, %rs11};
ret;
}
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