summaryrefslogtreecommitdiff
path: root/VRCSDK3Worlds/Assets/Editor/x64/Bakery/lmBatchPointLightProbeSH.ptx
diff options
context:
space:
mode:
Diffstat (limited to 'VRCSDK3Worlds/Assets/Editor/x64/Bakery/lmBatchPointLightProbeSH.ptx')
-rw-r--r--VRCSDK3Worlds/Assets/Editor/x64/Bakery/lmBatchPointLightProbeSH.ptx2378
1 files changed, 2378 insertions, 0 deletions
diff --git a/VRCSDK3Worlds/Assets/Editor/x64/Bakery/lmBatchPointLightProbeSH.ptx b/VRCSDK3Worlds/Assets/Editor/x64/Bakery/lmBatchPointLightProbeSH.ptx
new file mode 100644
index 00000000..885f3bf1
--- /dev/null
+++ b/VRCSDK3Worlds/Assets/Editor/x64/Bakery/lmBatchPointLightProbeSH.ptx
@@ -0,0 +1,2378 @@
+//
+// Generated by NVIDIA NVVM Compiler
+//
+// Compiler Build ID: CL-23083092
+// Cuda compilation tools, release 9.1, V9.1.85
+// Based on LLVM 3.4svn
+//
+
+.version 6.1
+.target sm_30
+.address_size 64
+
+ // .globl _Z6oxMainv
+.global .align 8 .b8 pixelID[8];
+.global .align 8 .b8 resolution[8];
+.global .align 4 .b8 normal[12];
+.global .align 4 .b8 camPos[12];
+.global .align 4 .b8 root[4];
+.global .align 4 .u32 imageEnabled;
+.global .texref lightmap;
+.global .align 16 .b8 tileInfo[16];
+.global .align 4 .u32 additive;
+.global .align 1 .b8 image[1];
+.global .align 1 .b8 image_HDR[1];
+.global .align 1 .b8 image_HDR2[1];
+.global .align 1 .b8 image_Mask[1];
+.global .align 1 .b8 image_RNM0[1];
+.global .align 1 .b8 image_RNM1[1];
+.global .align 1 .b8 image_RNM2[1];
+.global .align 1 .b8 image_RNM3[1];
+.global .align 1 .b8 uvpos[1];
+.global .align 1 .b8 uvnormal[1];
+.global .align 4 .u32 ignoreNormal;
+.global .align 1 .b8 localLights[1];
+.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo6normalE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo6camPosE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo4rootE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo12imageEnabledE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo8tileInfoE[8] = {82, 97, 121, 0, 16, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo8additiveE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo12ignoreNormalE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E;
+.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE;
+.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE;
+.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE;
+.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename6normalE[7] = {102, 108, 111, 97, 116, 51, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename6camPosE[7] = {102, 108, 111, 97, 116, 51, 0};
+.global .align 16 .b8 _ZN21rti_internal_typename4rootE[9] = {114, 116, 79, 98, 106, 101, 99, 116, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename12imageEnabledE[4] = {105, 110, 116, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename8tileInfoE[6] = {117, 105, 110, 116, 52, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename8additiveE[4] = {105, 110, 116, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename12ignoreNormalE[4] = {105, 110, 116, 0};
+.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum6normalE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum6camPosE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum4rootE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum12imageEnabledE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum8tileInfoE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum8additiveE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum12ignoreNormalE = 4919;
+.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0};
+.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0};
+.global .align 16 .b8 _ZN21rti_internal_semantic6normalE[17] = {97, 116, 116, 114, 105, 98, 117, 116, 101, 32, 110, 111, 114, 109, 97, 108, 0};
+.global .align 1 .b8 _ZN21rti_internal_semantic6camPosE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic4rootE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic12imageEnabledE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic8tileInfoE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic8additiveE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic12ignoreNormalE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation6normalE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation6camPosE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation4rootE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation12imageEnabledE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation8tileInfoE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation8additiveE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation12ignoreNormalE[1];
+
+.visible .entry _Z6oxMainv(
+
+)
+{
+ .local .align 4 .b8 __local_depot0[4];
+ .reg .b64 %SP;
+ .reg .b64 %SPL;
+ .reg .pred %p<136>;
+ .reg .b16 %rs<158>;
+ .reg .f32 %f<1391>;
+ .reg .b32 %r<248>;
+ .reg .b64 %rd<272>;
+
+
+ mov.u64 %rd271, __local_depot0;
+ cvta.local.u64 %SP, %rd271;
+ ld.global.v2.u32 {%r29, %r30}, [pixelID];
+ cvt.u64.u32 %rd10, %r29;
+ cvt.u64.u32 %rd11, %r30;
+ mov.u64 %rd14, uvnormal;
+ cvta.global.u64 %rd9, %rd14;
+ mov.u32 %r27, 2;
+ mov.u32 %r28, 4;
+ mov.u64 %rd13, 0;
+ // inline asm
+ call (%rd8), _rt_buffer_get_64, (%rd9, %r27, %r28, %rd10, %rd11, %rd13, %rd13);
+ // inline asm
+ ld.u32 %r1, [%rd8];
+ shr.u32 %r33, %r1, 16;
+ cvt.u16.u32 %rs1, %r33;
+ and.b16 %rs7, %rs1, 255;
+ cvt.u16.u32 %rs8, %r1;
+ or.b16 %rs9, %rs8, %rs7;
+ setp.eq.s16 %p8, %rs9, 0;
+ mov.f32 %f1300, 0f00000000;
+ mov.f32 %f1301, %f1300;
+ mov.f32 %f1302, %f1300;
+ @%p8 bra BB0_2;
+
+ ld.u8 %rs10, [%rd8+1];
+ and.b16 %rs12, %rs8, 255;
+ cvt.rn.f32.u16 %f262, %rs12;
+ div.rn.f32 %f263, %f262, 0f437F0000;
+ fma.rn.f32 %f264, %f263, 0f40000000, 0fBF800000;
+ cvt.rn.f32.u16 %f265, %rs10;
+ div.rn.f32 %f266, %f265, 0f437F0000;
+ fma.rn.f32 %f267, %f266, 0f40000000, 0fBF800000;
+ cvt.rn.f32.u16 %f268, %rs7;
+ div.rn.f32 %f269, %f268, 0f437F0000;
+ fma.rn.f32 %f270, %f269, 0f40000000, 0fBF800000;
+ mul.f32 %f271, %f267, %f267;
+ fma.rn.f32 %f272, %f264, %f264, %f271;
+ fma.rn.f32 %f273, %f270, %f270, %f272;
+ sqrt.rn.f32 %f274, %f273;
+ rcp.rn.f32 %f275, %f274;
+ mul.f32 %f1300, %f264, %f275;
+ mul.f32 %f1301, %f267, %f275;
+ mul.f32 %f1302, %f270, %f275;
+
+BB0_2:
+ ld.global.v2.u32 {%r34, %r35}, [pixelID];
+ ld.global.v2.u32 {%r37, %r38}, [tileInfo];
+ add.s32 %r2, %r34, %r37;
+ add.s32 %r3, %r35, %r38;
+ setp.eq.f32 %p9, %f1301, 0f00000000;
+ setp.eq.f32 %p10, %f1300, 0f00000000;
+ and.pred %p11, %p10, %p9;
+ setp.eq.f32 %p12, %f1302, 0f00000000;
+ and.pred %p13, %p11, %p12;
+ @%p13 bra BB0_104;
+ bra.uni BB0_3;
+
+BB0_104:
+ ld.global.u32 %r247, [imageEnabled];
+ and.b32 %r196, %r247, 1;
+ setp.eq.b32 %p127, %r196, 1;
+ @!%p127 bra BB0_106;
+ bra.uni BB0_105;
+
+BB0_105:
+ cvt.u64.u32 %rd159, %r2;
+ cvt.u64.u32 %rd160, %r3;
+ mov.u64 %rd163, image;
+ cvta.global.u64 %rd158, %rd163;
+ // inline asm
+ call (%rd157), _rt_buffer_get_64, (%rd158, %r27, %r28, %rd159, %rd160, %rd13, %rd13);
+ // inline asm
+ mov.u16 %rs90, 0;
+ st.v4.u8 [%rd157], {%rs90, %rs90, %rs90, %rs90};
+ ld.global.u32 %r247, [imageEnabled];
+
+BB0_106:
+ and.b32 %r199, %r247, 8;
+ setp.eq.s32 %p128, %r199, 0;
+ @%p128 bra BB0_108;
+
+ cvt.u64.u32 %rd167, %r3;
+ cvt.u64.u32 %rd166, %r2;
+ mov.u64 %rd170, image_Mask;
+ cvta.global.u64 %rd165, %rd170;
+ // inline asm
+ call (%rd164), _rt_buffer_get_64, (%rd165, %r27, %r27, %rd166, %rd167, %rd13, %rd13);
+ // inline asm
+ mov.f32 %f1264, 0f00000000;
+ cvt.rzi.u32.f32 %r202, %f1264;
+ cvt.u16.u32 %rs91, %r202;
+ mov.u16 %rs92, 0;
+ st.v2.u8 [%rd164], {%rs91, %rs92};
+ ld.global.u32 %r247, [imageEnabled];
+
+BB0_108:
+ cvt.u64.u32 %rd6, %r2;
+ cvt.u64.u32 %rd7, %r3;
+ and.b32 %r203, %r247, 4;
+ setp.eq.s32 %p129, %r203, 0;
+ @%p129 bra BB0_112;
+
+ ld.global.u32 %r204, [additive];
+ setp.eq.s32 %p130, %r204, 0;
+ @%p130 bra BB0_111;
+
+ mov.u64 %rd183, image_HDR;
+ cvta.global.u64 %rd172, %rd183;
+ mov.u32 %r208, 8;
+ // inline asm
+ call (%rd171), _rt_buffer_get_64, (%rd172, %r27, %r208, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ ld.v4.u16 {%rs99, %rs100, %rs101, %rs102}, [%rd171];
+ // inline asm
+ { cvt.f32.f16 %f1265, %rs99;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1266, %rs100;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1267, %rs101;}
+
+ // inline asm
+ // inline asm
+ call (%rd177), _rt_buffer_get_64, (%rd172, %r27, %r208, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ add.f32 %f1268, %f1265, 0f00000000;
+ add.f32 %f1269, %f1266, 0f00000000;
+ add.f32 %f1270, %f1267, 0f00000000;
+ // inline asm
+ { cvt.rn.f16.f32 %rs98, %f1270;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs97, %f1269;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs96, %f1268;}
+
+ // inline asm
+ mov.u16 %rs103, 0;
+ st.v4.u16 [%rd177], {%rs96, %rs97, %rs98, %rs103};
+ bra.uni BB0_112;
+
+BB0_3:
+ ld.global.v2.u32 {%r46, %r47}, [pixelID];
+ cvt.u64.u32 %rd17, %r46;
+ cvt.u64.u32 %rd18, %r47;
+ mov.u64 %rd26, uvpos;
+ cvta.global.u64 %rd16, %rd26;
+ mov.u32 %r43, 12;
+ // inline asm
+ call (%rd15), _rt_buffer_get_64, (%rd16, %r27, %r43, %rd17, %rd18, %rd13, %rd13);
+ // inline asm
+ ld.f32 %f9, [%rd15+8];
+ ld.f32 %f8, [%rd15+4];
+ ld.f32 %f7, [%rd15];
+ mul.f32 %f292, %f7, 0f3456BF95;
+ mul.f32 %f293, %f8, 0f3456BF95;
+ mul.f32 %f294, %f9, 0f3456BF95;
+ abs.f32 %f295, %f1300;
+ div.rn.f32 %f296, %f292, %f295;
+ abs.f32 %f297, %f1301;
+ div.rn.f32 %f298, %f293, %f297;
+ abs.f32 %f299, %f1302;
+ div.rn.f32 %f300, %f294, %f299;
+ abs.f32 %f301, %f296;
+ abs.f32 %f302, %f298;
+ abs.f32 %f303, %f300;
+ mov.f32 %f304, 0f38D1B717;
+ max.f32 %f305, %f301, %f304;
+ max.f32 %f306, %f302, %f304;
+ max.f32 %f307, %f303, %f304;
+ fma.rn.f32 %f10, %f1300, %f305, %f7;
+ fma.rn.f32 %f11, %f1301, %f306, %f8;
+ fma.rn.f32 %f12, %f1302, %f307, %f9;
+ mov.u64 %rd27, localLights;
+ cvta.global.u64 %rd25, %rd27;
+ mov.u32 %r44, 1;
+ mov.u32 %r45, 96;
+ // inline asm
+ call (%rd21, %rd22, %rd23, %rd24), _rt_buffer_get_size_64, (%rd25, %r44, %r45);
+ // inline asm
+ cvt.u32.u64 %r4, %rd21;
+ setp.eq.s32 %p14, %r4, 0;
+ mov.f32 %f1303, 0f00000000;
+ mov.f32 %f1304, %f1303;
+ mov.f32 %f1305, %f1303;
+ mov.f32 %f1306, %f1303;
+ mov.f32 %f1307, %f1303;
+ mov.f32 %f1308, %f1303;
+ mov.f32 %f1309, %f1303;
+ mov.f32 %f1310, %f1303;
+ mov.f32 %f1311, %f1303;
+ mov.f32 %f1312, %f1303;
+ mov.f32 %f1313, %f1303;
+ mov.f32 %f1314, %f1303;
+ mov.f32 %f1315, %f1303;
+ mov.f32 %f1316, %f1303;
+ mov.f32 %f1317, %f1303;
+ mov.f32 %f1318, %f1303;
+ @%p14 bra BB0_40;
+
+ mov.f32 %f324, 0f40000000;
+ cvt.rzi.f32.f32 %f325, %f324;
+ add.f32 %f326, %f325, %f325;
+ mov.f32 %f327, 0f40800000;
+ sub.f32 %f328, %f327, %f326;
+ abs.f32 %f13, %f328;
+ mul.f32 %f14, %f10, 0f3456BF95;
+ mul.f32 %f15, %f11, 0f3456BF95;
+ mul.f32 %f16, %f12, 0f3456BF95;
+ mov.f32 %f323, 0f00000000;
+ mov.u32 %r239, 0;
+ abs.f32 %f516, %f14;
+ abs.f32 %f517, %f15;
+ max.f32 %f518, %f516, %f517;
+ abs.f32 %f519, %f16;
+ max.f32 %f520, %f518, %f519;
+ mov.f32 %f1303, %f323;
+ mov.f32 %f1304, %f323;
+ mov.f32 %f1305, %f323;
+ mov.f32 %f1306, %f323;
+ mov.f32 %f1307, %f323;
+ mov.f32 %f1308, %f323;
+ mov.f32 %f1309, %f323;
+ mov.f32 %f1310, %f323;
+ mov.f32 %f1311, %f323;
+ mov.f32 %f1312, %f323;
+ mov.f32 %f1313, %f323;
+ mov.f32 %f1314, %f323;
+ mov.f32 %f1315, %f323;
+ mov.f32 %f1316, %f323;
+ mov.f32 %f1317, %f323;
+ mov.f32 %f1318, %f323;
+
+BB0_5:
+ cvt.u64.u32 %rd30, %r239;
+ // inline asm
+ call (%rd28), _rt_buffer_get_64, (%rd25, %r44, %r45, %rd30, %rd13, %rd13, %rd13);
+ // inline asm
+ ld.v4.f32 {%f331, %f332, %f333, %f334}, [%rd28+80];
+ ld.v4.f32 {%f335, %f336, %f337, %f338}, [%rd28+64];
+ ld.v4.f32 {%f339, %f340, %f341, %f342}, [%rd28+48];
+ ld.v4.f32 {%f1322, %f1323, %f1324, %f346}, [%rd28+32];
+ ld.v4.f32 {%f347, %f348, %f349, %f350}, [%rd28+16];
+ ld.v4.f32 {%f351, %f352, %f353, %f354}, [%rd28];
+ mov.b32 %r6, %f334;
+ sub.f32 %f356, %f352, %f7;
+ sub.f32 %f357, %f353, %f8;
+ sub.f32 %f358, %f354, %f9;
+ mul.f32 %f359, %f357, %f357;
+ fma.rn.f32 %f360, %f356, %f356, %f359;
+ fma.rn.f32 %f361, %f358, %f358, %f360;
+ sqrt.rn.f32 %f59, %f361;
+ rcp.rn.f32 %f362, %f59;
+ mul.f32 %f60, %f356, %f362;
+ mul.f32 %f61, %f357, %f362;
+ mul.f32 %f62, %f358, %f362;
+ mul.f32 %f63, %f59, %f350;
+ abs.f32 %f64, %f63;
+ setp.lt.f32 %p15, %f64, 0f00800000;
+ mul.f32 %f363, %f64, 0f4B800000;
+ selp.f32 %f364, 0fC3170000, 0fC2FE0000, %p15;
+ selp.f32 %f365, %f363, %f64, %p15;
+ mov.b32 %r53, %f365;
+ and.b32 %r54, %r53, 8388607;
+ or.b32 %r55, %r54, 1065353216;
+ mov.b32 %f366, %r55;
+ shr.u32 %r56, %r53, 23;
+ cvt.rn.f32.u32 %f367, %r56;
+ add.f32 %f368, %f364, %f367;
+ setp.gt.f32 %p16, %f366, 0f3FB504F3;
+ mul.f32 %f369, %f366, 0f3F000000;
+ add.f32 %f370, %f368, 0f3F800000;
+ selp.f32 %f371, %f369, %f366, %p16;
+ selp.f32 %f372, %f370, %f368, %p16;
+ add.f32 %f373, %f371, 0fBF800000;
+ add.f32 %f330, %f371, 0f3F800000;
+ // inline asm
+ rcp.approx.ftz.f32 %f329,%f330;
+ // inline asm
+ add.f32 %f374, %f373, %f373;
+ mul.f32 %f375, %f329, %f374;
+ mul.f32 %f376, %f375, %f375;
+ mov.f32 %f377, 0f3C4CAF63;
+ mov.f32 %f378, 0f3B18F0FE;
+ fma.rn.f32 %f379, %f378, %f376, %f377;
+ mov.f32 %f380, 0f3DAAAABD;
+ fma.rn.f32 %f381, %f379, %f376, %f380;
+ mul.rn.f32 %f382, %f381, %f376;
+ mul.rn.f32 %f383, %f382, %f375;
+ sub.f32 %f384, %f373, %f375;
+ neg.f32 %f385, %f375;
+ add.f32 %f386, %f384, %f384;
+ fma.rn.f32 %f387, %f385, %f373, %f386;
+ mul.rn.f32 %f388, %f329, %f387;
+ add.f32 %f389, %f383, %f375;
+ sub.f32 %f390, %f375, %f389;
+ add.f32 %f391, %f383, %f390;
+ add.f32 %f392, %f388, %f391;
+ add.f32 %f393, %f389, %f392;
+ sub.f32 %f394, %f389, %f393;
+ add.f32 %f395, %f392, %f394;
+ mov.f32 %f396, 0f3F317200;
+ mul.rn.f32 %f397, %f372, %f396;
+ mov.f32 %f398, 0f35BFBE8E;
+ mul.rn.f32 %f399, %f372, %f398;
+ add.f32 %f400, %f397, %f393;
+ sub.f32 %f401, %f397, %f400;
+ add.f32 %f402, %f393, %f401;
+ add.f32 %f403, %f395, %f402;
+ add.f32 %f404, %f399, %f403;
+ add.f32 %f405, %f400, %f404;
+ sub.f32 %f406, %f400, %f405;
+ add.f32 %f407, %f404, %f406;
+ mul.rn.f32 %f65, %f327, %f405;
+ neg.f32 %f409, %f65;
+ fma.rn.f32 %f410, %f327, %f405, %f409;
+ fma.rn.f32 %f411, %f327, %f407, %f410;
+ fma.rn.f32 %f66, %f323, %f405, %f411;
+ add.rn.f32 %f67, %f65, %f66;
+ mov.b32 %r57, %f67;
+ setp.eq.s32 %p1, %r57, 1118925336;
+ add.s32 %r58, %r57, -1;
+ mov.b32 %f413, %r58;
+ selp.f32 %f414, %f413, %f67, %p1;
+ mul.f32 %f415, %f414, 0f3FB8AA3B;
+ cvt.rzi.f32.f32 %f416, %f415;
+ mov.f32 %f417, 0fBF317200;
+ fma.rn.f32 %f418, %f416, %f417, %f414;
+ mov.f32 %f419, 0fB5BFBE8E;
+ fma.rn.f32 %f420, %f416, %f419, %f418;
+ mul.f32 %f421, %f420, 0f3FB8AA3B;
+ ex2.approx.ftz.f32 %f422, %f421;
+ add.f32 %f423, %f416, 0f00000000;
+ ex2.approx.f32 %f424, %f423;
+ mul.f32 %f425, %f422, %f424;
+ setp.lt.f32 %p17, %f414, 0fC2D20000;
+ selp.f32 %f426, 0f00000000, %f425, %p17;
+ setp.gt.f32 %p18, %f414, 0f42D20000;
+ selp.f32 %f1319, 0f7F800000, %f426, %p18;
+ setp.eq.f32 %p19, %f1319, 0f7F800000;
+ @%p19 bra BB0_7;
+
+ neg.f32 %f427, %f67;
+ add.rn.f32 %f428, %f65, %f427;
+ add.rn.f32 %f429, %f428, %f66;
+ add.f32 %f430, %f429, 0f37000000;
+ selp.f32 %f431, %f430, %f429, %p1;
+ fma.rn.f32 %f1319, %f1319, %f431, %f1319;
+
+BB0_7:
+ setp.lt.f32 %p20, %f63, 0f00000000;
+ setp.eq.f32 %p21, %f13, 0f3F800000;
+ and.pred %p2, %p20, %p21;
+ mov.b32 %r59, %f1319;
+ xor.b32 %r60, %r59, -2147483648;
+ mov.b32 %f432, %r60;
+ selp.f32 %f1321, %f432, %f1319, %p2;
+ setp.eq.f32 %p22, %f63, 0f00000000;
+ @%p22 bra BB0_10;
+ bra.uni BB0_8;
+
+BB0_10:
+ add.f32 %f435, %f63, %f63;
+ selp.f32 %f1321, %f435, 0f00000000, %p21;
+ bra.uni BB0_11;
+
+BB0_8:
+ setp.geu.f32 %p23, %f63, 0f00000000;
+ @%p23 bra BB0_11;
+
+ cvt.rzi.f32.f32 %f434, %f327;
+ setp.neu.f32 %p24, %f434, 0f40800000;
+ selp.f32 %f1321, 0f7FFFFFFF, %f1321, %p24;
+
+BB0_11:
+ add.f32 %f436, %f64, 0f40800000;
+ mov.b32 %r61, %f436;
+ setp.lt.s32 %p26, %r61, 2139095040;
+ @%p26 bra BB0_16;
+
+ setp.gtu.f32 %p27, %f64, 0f7F800000;
+ @%p27 bra BB0_15;
+ bra.uni BB0_13;
+
+BB0_15:
+ add.f32 %f1321, %f63, 0f40800000;
+ bra.uni BB0_16;
+
+BB0_13:
+ setp.neu.f32 %p28, %f64, 0f7F800000;
+ @%p28 bra BB0_16;
+
+ selp.f32 %f1321, 0fFF800000, 0f7F800000, %p2;
+
+BB0_16:
+ mul.f32 %f437, %f59, %f348;
+ mov.f32 %f1346, 0f3F800000;
+ sub.f32 %f439, %f1346, %f1321;
+ setp.eq.f32 %p29, %f63, 0f3F800000;
+ selp.f32 %f440, 0f00000000, %f439, %p29;
+ cvt.sat.f32.f32 %f441, %f440;
+ fma.rn.f32 %f442, %f437, %f437, %f349;
+ div.rn.f32 %f1325, %f441, %f442;
+ mul.f32 %f443, %f1301, %f61;
+ fma.rn.f32 %f444, %f1300, %f60, %f443;
+ fma.rn.f32 %f94, %f1302, %f62, %f444;
+ setp.eq.f32 %p30, %f351, 0f3F800000;
+ @%p30 bra BB0_22;
+ bra.uni BB0_17;
+
+BB0_22:
+ setp.leu.f32 %p34, %f346, 0f00000000;
+ @%p34 bra BB0_24;
+
+ mul.f32 %f475, %f331, %f60;
+ mul.f32 %f476, %f332, %f61;
+ neg.f32 %f477, %f476;
+ sub.f32 %f478, %f477, %f475;
+ mul.f32 %f479, %f333, %f62;
+ sub.f32 %f480, %f478, %f479;
+ setp.gt.f32 %p35, %f480, 0f00000000;
+ selp.f32 %f481, 0f3F800000, 0f00000000, %p35;
+ mul.f32 %f482, %f340, %f61;
+ fma.rn.f32 %f483, %f339, %f60, %f482;
+ mul.f32 %f484, %f336, %f61;
+ fma.rn.f32 %f485, %f335, %f60, %f484;
+ fma.rn.f32 %f486, %f341, %f62, %f483;
+ fma.rn.f32 %f487, %f337, %f62, %f485;
+ fma.rn.f32 %f471, %f342, %f486, 0f3F000000;
+ fma.rn.f32 %f472, %f342, %f487, 0f3F000000;
+ cvt.rzi.s32.f32 %r65, %f346;
+ mov.f32 %f474, 0f00000000;
+ // inline asm
+ call (%f467, %f468, %f469, %f470), _rt_texture_get_f_id, (%r65, %r27, %f471, %f472, %f474, %f474);
+ // inline asm
+ mul.f32 %f488, %f481, %f467;
+ mul.f32 %f489, %f481, %f468;
+ mul.f32 %f490, %f481, %f469;
+ mul.f32 %f1322, %f1322, %f488;
+ mul.f32 %f1323, %f1323, %f489;
+ mul.f32 %f1324, %f1324, %f490;
+ bra.uni BB0_24;
+
+BB0_17:
+ setp.eq.f32 %p31, %f351, 0f40000000;
+ @%p31 bra BB0_20;
+ bra.uni BB0_18;
+
+BB0_20:
+ setp.leu.f32 %p33, %f346, 0f00000000;
+ @%p33 bra BB0_24;
+
+ mul.f32 %f461, %f340, %f61;
+ fma.rn.f32 %f462, %f339, %f60, %f461;
+ mul.f32 %f463, %f336, %f61;
+ fma.rn.f32 %f464, %f335, %f60, %f463;
+ mul.f32 %f465, %f332, %f61;
+ fma.rn.f32 %f466, %f331, %f60, %f465;
+ fma.rn.f32 %f458, %f341, %f62, %f462;
+ fma.rn.f32 %f459, %f337, %f62, %f464;
+ fma.rn.f32 %f460, %f333, %f62, %f466;
+ cvt.rzi.s32.f32 %r62, %f346;
+ mov.u32 %r63, 6;
+ mov.u32 %r64, 0;
+ // inline asm
+ call (%f454, %f455, %f456, %f457), _rt_texture_get_base_id, (%r62, %r63, %f458, %f459, %f460, %r64);
+ // inline asm
+ mul.f32 %f1322, %f1322, %f454;
+ mul.f32 %f1323, %f1323, %f455;
+ mul.f32 %f1324, %f1324, %f456;
+ bra.uni BB0_24;
+
+BB0_18:
+ setp.neu.f32 %p32, %f351, 0f40800000;
+ @%p32 bra BB0_24;
+
+ mul.f32 %f445, %f331, %f60;
+ mul.f32 %f446, %f332, %f61;
+ neg.f32 %f447, %f446;
+ sub.f32 %f448, %f447, %f445;
+ mul.f32 %f449, %f333, %f62;
+ sub.f32 %f450, %f448, %f449;
+ fma.rn.f32 %f451, %f346, %f450, %f342;
+ cvt.sat.f32.f32 %f452, %f451;
+ mul.f32 %f453, %f452, %f452;
+ mul.f32 %f1325, %f1325, %f453;
+
+BB0_24:
+ max.f32 %f506, %f1322, %f1323;
+ max.f32 %f507, %f506, %f1324;
+ mul.f32 %f508, %f1325, %f507;
+ setp.lt.f32 %p37, %f508, 0f3727C5AC;
+ mov.pred %p135, -1;
+ mov.f32 %f1326, 0f00000000;
+ mov.f32 %f1327, %f1326;
+ mov.f32 %f1328, %f1326;
+ mov.f32 %f1329, %f1326;
+ mov.f32 %f1330, %f1326;
+ mov.f32 %f1331, %f1326;
+ mov.f32 %f1332, %f1326;
+ mov.f32 %f1333, %f1326;
+ mov.f32 %f1334, %f1326;
+ mov.f32 %f1335, %f1326;
+ mov.f32 %f1336, %f1326;
+ mov.f32 %f1337, %f1326;
+ mov.f32 %f1338, %f1326;
+ mov.f32 %f1339, %f1326;
+ mov.f32 %f1340, %f1326;
+ @%p37 bra BB0_26;
+
+ ld.global.u32 %r67, [ignoreNormal];
+ setp.eq.s32 %p39, %r67, 0;
+ selp.f32 %f509, %f94, 0f3F800000, %p39;
+ cvt.sat.f32.f32 %f510, %f509;
+ mul.f32 %f511, %f1325, %f510;
+ mul.f32 %f1326, %f1322, %f511;
+ mul.f32 %f1327, %f1323, %f511;
+ mul.f32 %f1328, %f1324, %f511;
+ mul.f32 %f512, %f1325, 0f3E800000;
+ mul.f32 %f1329, %f1322, %f512;
+ mul.f32 %f1330, %f1323, %f512;
+ mul.f32 %f1331, %f1324, %f512;
+ mul.f32 %f1332, %f60, %f1329;
+ mul.f32 %f1333, %f60, %f1330;
+ mul.f32 %f1334, %f60, %f1331;
+ mul.f32 %f1335, %f61, %f1329;
+ mul.f32 %f1336, %f61, %f1330;
+ mul.f32 %f1337, %f61, %f1331;
+ mul.f32 %f1338, %f62, %f1329;
+ mul.f32 %f1339, %f62, %f1330;
+ mul.f32 %f1340, %f62, %f1331;
+ mov.pred %p135, 0;
+
+BB0_26:
+ @%p135 bra BB0_39;
+
+ setp.eq.s32 %p40, %r6, 0;
+ @%p40 bra BB0_38;
+
+ mov.f32 %f1345, 0f00000000;
+ setp.lt.s32 %p41, %r6, 1;
+ @%p41 bra BB0_37;
+
+ max.f32 %f137, %f520, %f304;
+ and.b32 %r8, %r6, 3;
+ setp.eq.s32 %p42, %r8, 0;
+ add.u64 %rd35, %SP, 0;
+ cvta.to.local.u64 %rd2, %rd35;
+ mov.f32 %f1345, 0f00000000;
+ mov.u32 %r243, 0;
+ @%p42 bra BB0_35;
+
+ setp.eq.s32 %p43, %r8, 1;
+ mov.f32 %f1342, 0f00000000;
+ mov.u32 %r241, 0;
+ @%p43 bra BB0_34;
+
+ setp.eq.s32 %p44, %r8, 2;
+ mov.f32 %f1341, 0f00000000;
+ mov.u32 %r240, 0;
+ @%p44 bra BB0_33;
+
+ sub.f32 %f532, %f352, %f347;
+ sub.f32 %f533, %f353, %f347;
+ sub.f32 %f534, %f354, %f347;
+ sub.f32 %f535, %f532, %f7;
+ sub.f32 %f536, %f533, %f8;
+ sub.f32 %f537, %f534, %f9;
+ mul.f32 %f538, %f536, %f536;
+ fma.rn.f32 %f539, %f535, %f535, %f538;
+ fma.rn.f32 %f540, %f537, %f537, %f539;
+ sqrt.rn.f32 %f531, %f540;
+ rcp.rn.f32 %f541, %f531;
+ mul.f32 %f527, %f541, %f535;
+ mul.f32 %f528, %f541, %f536;
+ mul.f32 %f529, %f541, %f537;
+ ld.global.u32 %r75, [imageEnabled];
+ and.b32 %r76, %r75, 32;
+ setp.eq.s32 %p45, %r76, 0;
+ selp.f32 %f542, 0f3F800000, 0f41200000, %p45;
+ mul.f32 %f530, %f542, %f137;
+ mov.u32 %r77, 1065353216;
+ st.local.u32 [%rd2], %r77;
+ ld.global.u32 %r71, [root];
+ // inline asm
+ call _rt_trace_64, (%r71, %f10, %f11, %f12, %f527, %f528, %f529, %r44, %f530, %f531, %rd35, %r28);
+ // inline asm
+ ld.local.f32 %f543, [%rd2];
+ add.f32 %f1341, %f543, 0f00000000;
+ mov.u32 %r240, %r44;
+
+BB0_33:
+ cvt.rn.f32.s32 %f552, %r240;
+ mul.f32 %f553, %f552, 0f3DD32618;
+ cvt.rmi.f32.f32 %f554, %f553;
+ sub.f32 %f555, %f553, %f554;
+ mul.f32 %f556, %f552, 0f3DD2F1AA;
+ cvt.rmi.f32.f32 %f557, %f556;
+ sub.f32 %f558, %f556, %f557;
+ mul.f32 %f559, %f552, 0f3DC74539;
+ cvt.rmi.f32.f32 %f560, %f559;
+ sub.f32 %f561, %f559, %f560;
+ add.f32 %f562, %f558, 0f4199851F;
+ add.f32 %f563, %f561, 0f4199851F;
+ add.f32 %f564, %f555, 0f4199851F;
+ mul.f32 %f565, %f558, %f563;
+ fma.rn.f32 %f566, %f555, %f562, %f565;
+ fma.rn.f32 %f567, %f564, %f561, %f566;
+ add.f32 %f568, %f555, %f567;
+ add.f32 %f569, %f558, %f567;
+ add.f32 %f570, %f561, %f567;
+ add.f32 %f571, %f568, %f569;
+ mul.f32 %f572, %f570, %f571;
+ cvt.rmi.f32.f32 %f573, %f572;
+ sub.f32 %f574, %f572, %f573;
+ add.f32 %f575, %f568, %f570;
+ mul.f32 %f576, %f569, %f575;
+ cvt.rmi.f32.f32 %f577, %f576;
+ sub.f32 %f578, %f576, %f577;
+ add.f32 %f579, %f569, %f570;
+ mul.f32 %f580, %f568, %f579;
+ cvt.rmi.f32.f32 %f581, %f580;
+ sub.f32 %f582, %f580, %f581;
+ fma.rn.f32 %f583, %f574, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f584, %f578, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f585, %f582, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f586, %f347, %f583, %f352;
+ fma.rn.f32 %f587, %f347, %f584, %f353;
+ fma.rn.f32 %f588, %f347, %f585, %f354;
+ sub.f32 %f589, %f586, %f7;
+ sub.f32 %f590, %f587, %f8;
+ sub.f32 %f591, %f588, %f9;
+ mul.f32 %f592, %f590, %f590;
+ fma.rn.f32 %f593, %f589, %f589, %f592;
+ fma.rn.f32 %f594, %f591, %f591, %f593;
+ sqrt.rn.f32 %f551, %f594;
+ rcp.rn.f32 %f595, %f551;
+ mul.f32 %f547, %f595, %f589;
+ mul.f32 %f548, %f595, %f590;
+ mul.f32 %f549, %f595, %f591;
+ ld.global.u32 %r81, [imageEnabled];
+ and.b32 %r82, %r81, 32;
+ setp.eq.s32 %p46, %r82, 0;
+ selp.f32 %f596, 0f3F800000, 0f41200000, %p46;
+ mul.f32 %f550, %f596, %f137;
+ mov.u32 %r83, 1065353216;
+ st.local.u32 [%rd2], %r83;
+ ld.global.u32 %r78, [root];
+ // inline asm
+ call _rt_trace_64, (%r78, %f10, %f11, %f12, %f547, %f548, %f549, %r44, %f550, %f551, %rd35, %r28);
+ // inline asm
+ ld.local.f32 %f597, [%rd2];
+ add.f32 %f1342, %f1341, %f597;
+ add.s32 %r241, %r240, 1;
+
+BB0_34:
+ cvt.rn.f32.s32 %f606, %r241;
+ mul.f32 %f607, %f606, 0f3DD32618;
+ cvt.rmi.f32.f32 %f608, %f607;
+ sub.f32 %f609, %f607, %f608;
+ mul.f32 %f610, %f606, 0f3DD2F1AA;
+ cvt.rmi.f32.f32 %f611, %f610;
+ sub.f32 %f612, %f610, %f611;
+ mul.f32 %f613, %f606, 0f3DC74539;
+ cvt.rmi.f32.f32 %f614, %f613;
+ sub.f32 %f615, %f613, %f614;
+ add.f32 %f616, %f612, 0f4199851F;
+ add.f32 %f617, %f615, 0f4199851F;
+ add.f32 %f618, %f609, 0f4199851F;
+ mul.f32 %f619, %f612, %f617;
+ fma.rn.f32 %f620, %f609, %f616, %f619;
+ fma.rn.f32 %f621, %f618, %f615, %f620;
+ add.f32 %f622, %f609, %f621;
+ add.f32 %f623, %f612, %f621;
+ add.f32 %f624, %f615, %f621;
+ add.f32 %f625, %f622, %f623;
+ mul.f32 %f626, %f624, %f625;
+ cvt.rmi.f32.f32 %f627, %f626;
+ sub.f32 %f628, %f626, %f627;
+ add.f32 %f629, %f622, %f624;
+ mul.f32 %f630, %f623, %f629;
+ cvt.rmi.f32.f32 %f631, %f630;
+ sub.f32 %f632, %f630, %f631;
+ add.f32 %f633, %f623, %f624;
+ mul.f32 %f634, %f622, %f633;
+ cvt.rmi.f32.f32 %f635, %f634;
+ sub.f32 %f636, %f634, %f635;
+ fma.rn.f32 %f637, %f628, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f638, %f632, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f639, %f636, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f640, %f347, %f637, %f352;
+ fma.rn.f32 %f641, %f347, %f638, %f353;
+ fma.rn.f32 %f642, %f347, %f639, %f354;
+ sub.f32 %f643, %f640, %f7;
+ sub.f32 %f644, %f641, %f8;
+ sub.f32 %f645, %f642, %f9;
+ mul.f32 %f646, %f644, %f644;
+ fma.rn.f32 %f647, %f643, %f643, %f646;
+ fma.rn.f32 %f648, %f645, %f645, %f647;
+ sqrt.rn.f32 %f605, %f648;
+ rcp.rn.f32 %f649, %f605;
+ mul.f32 %f601, %f649, %f643;
+ mul.f32 %f602, %f649, %f644;
+ mul.f32 %f603, %f649, %f645;
+ ld.global.u32 %r87, [imageEnabled];
+ and.b32 %r88, %r87, 32;
+ setp.eq.s32 %p47, %r88, 0;
+ selp.f32 %f650, 0f3F800000, 0f41200000, %p47;
+ mul.f32 %f604, %f650, %f137;
+ mov.u32 %r89, 1065353216;
+ st.local.u32 [%rd2], %r89;
+ ld.global.u32 %r84, [root];
+ mov.u32 %r85, 1;
+ // inline asm
+ call _rt_trace_64, (%r84, %f10, %f11, %f12, %f601, %f602, %f603, %r85, %f604, %f605, %rd35, %r28);
+ // inline asm
+ ld.local.f32 %f651, [%rd2];
+ add.f32 %f1345, %f1342, %f651;
+ add.s32 %r243, %r241, 1;
+
+BB0_35:
+ setp.lt.u32 %p48, %r6, 4;
+ @%p48 bra BB0_37;
+
+BB0_36:
+ cvt.rn.f32.s32 %f684, %r243;
+ mul.f32 %f685, %f684, 0f3DD32618;
+ cvt.rmi.f32.f32 %f686, %f685;
+ sub.f32 %f687, %f685, %f686;
+ mul.f32 %f688, %f684, 0f3DD2F1AA;
+ cvt.rmi.f32.f32 %f689, %f688;
+ sub.f32 %f690, %f688, %f689;
+ mul.f32 %f691, %f684, 0f3DC74539;
+ cvt.rmi.f32.f32 %f692, %f691;
+ sub.f32 %f693, %f691, %f692;
+ add.f32 %f694, %f690, 0f4199851F;
+ add.f32 %f695, %f693, 0f4199851F;
+ add.f32 %f696, %f687, 0f4199851F;
+ mul.f32 %f697, %f690, %f695;
+ fma.rn.f32 %f698, %f687, %f694, %f697;
+ fma.rn.f32 %f699, %f696, %f693, %f698;
+ add.f32 %f700, %f687, %f699;
+ add.f32 %f701, %f690, %f699;
+ add.f32 %f702, %f693, %f699;
+ add.f32 %f703, %f700, %f701;
+ mul.f32 %f704, %f702, %f703;
+ cvt.rmi.f32.f32 %f705, %f704;
+ sub.f32 %f706, %f704, %f705;
+ add.f32 %f707, %f700, %f702;
+ mul.f32 %f708, %f701, %f707;
+ cvt.rmi.f32.f32 %f709, %f708;
+ sub.f32 %f710, %f708, %f709;
+ add.f32 %f711, %f701, %f702;
+ mul.f32 %f712, %f700, %f711;
+ cvt.rmi.f32.f32 %f713, %f712;
+ sub.f32 %f714, %f712, %f713;
+ fma.rn.f32 %f715, %f706, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f716, %f710, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f717, %f714, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f718, %f347, %f715, %f352;
+ fma.rn.f32 %f719, %f347, %f716, %f353;
+ fma.rn.f32 %f720, %f347, %f717, %f354;
+ sub.f32 %f721, %f718, %f7;
+ sub.f32 %f722, %f719, %f8;
+ sub.f32 %f723, %f720, %f9;
+ mul.f32 %f724, %f722, %f722;
+ fma.rn.f32 %f725, %f721, %f721, %f724;
+ fma.rn.f32 %f726, %f723, %f723, %f725;
+ sqrt.rn.f32 %f659, %f726;
+ rcp.rn.f32 %f727, %f659;
+ mul.f32 %f655, %f727, %f721;
+ mul.f32 %f656, %f727, %f722;
+ mul.f32 %f657, %f727, %f723;
+ ld.global.u32 %r102, [imageEnabled];
+ and.b32 %r103, %r102, 32;
+ setp.eq.s32 %p49, %r103, 0;
+ selp.f32 %f728, 0f3F800000, 0f41200000, %p49;
+ mul.f32 %f658, %f728, %f137;
+ mov.u32 %r104, 1065353216;
+ st.local.u32 [%rd2], %r104;
+ ld.global.u32 %r90, [root];
+ mov.u32 %r100, 1;
+ // inline asm
+ call _rt_trace_64, (%r90, %f10, %f11, %f12, %f655, %f656, %f657, %r100, %f658, %f659, %rd35, %r28);
+ // inline asm
+ ld.local.f32 %f729, [%rd2];
+ add.f32 %f730, %f1345, %f729;
+ add.s32 %r105, %r243, 1;
+ cvt.rn.f32.s32 %f731, %r105;
+ mul.f32 %f732, %f731, 0f3DD32618;
+ cvt.rmi.f32.f32 %f733, %f732;
+ sub.f32 %f734, %f732, %f733;
+ mul.f32 %f735, %f731, 0f3DD2F1AA;
+ cvt.rmi.f32.f32 %f736, %f735;
+ sub.f32 %f737, %f735, %f736;
+ mul.f32 %f738, %f731, 0f3DC74539;
+ cvt.rmi.f32.f32 %f739, %f738;
+ sub.f32 %f740, %f738, %f739;
+ add.f32 %f741, %f737, 0f4199851F;
+ add.f32 %f742, %f740, 0f4199851F;
+ add.f32 %f743, %f734, 0f4199851F;
+ mul.f32 %f744, %f737, %f742;
+ fma.rn.f32 %f745, %f734, %f741, %f744;
+ fma.rn.f32 %f746, %f743, %f740, %f745;
+ add.f32 %f747, %f734, %f746;
+ add.f32 %f748, %f737, %f746;
+ add.f32 %f749, %f740, %f746;
+ add.f32 %f750, %f747, %f748;
+ mul.f32 %f751, %f749, %f750;
+ cvt.rmi.f32.f32 %f752, %f751;
+ sub.f32 %f753, %f751, %f752;
+ add.f32 %f754, %f747, %f749;
+ mul.f32 %f755, %f748, %f754;
+ cvt.rmi.f32.f32 %f756, %f755;
+ sub.f32 %f757, %f755, %f756;
+ add.f32 %f758, %f748, %f749;
+ mul.f32 %f759, %f747, %f758;
+ cvt.rmi.f32.f32 %f760, %f759;
+ sub.f32 %f761, %f759, %f760;
+ fma.rn.f32 %f762, %f753, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f763, %f757, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f764, %f761, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f765, %f347, %f762, %f352;
+ fma.rn.f32 %f766, %f347, %f763, %f353;
+ fma.rn.f32 %f767, %f347, %f764, %f354;
+ sub.f32 %f768, %f765, %f7;
+ sub.f32 %f769, %f766, %f8;
+ sub.f32 %f770, %f767, %f9;
+ mul.f32 %f771, %f769, %f769;
+ fma.rn.f32 %f772, %f768, %f768, %f771;
+ fma.rn.f32 %f773, %f770, %f770, %f772;
+ sqrt.rn.f32 %f667, %f773;
+ rcp.rn.f32 %f774, %f667;
+ mul.f32 %f663, %f774, %f768;
+ mul.f32 %f664, %f774, %f769;
+ mul.f32 %f665, %f774, %f770;
+ ld.global.u32 %r106, [imageEnabled];
+ and.b32 %r107, %r106, 32;
+ setp.eq.s32 %p50, %r107, 0;
+ selp.f32 %f775, 0f3F800000, 0f41200000, %p50;
+ mul.f32 %f666, %f775, %f137;
+ st.local.u32 [%rd2], %r104;
+ ld.global.u32 %r93, [root];
+ // inline asm
+ call _rt_trace_64, (%r93, %f10, %f11, %f12, %f663, %f664, %f665, %r100, %f666, %f667, %rd35, %r28);
+ // inline asm
+ ld.local.f32 %f776, [%rd2];
+ add.f32 %f777, %f730, %f776;
+ add.s32 %r108, %r243, 2;
+ cvt.rn.f32.s32 %f778, %r108;
+ mul.f32 %f779, %f778, 0f3DD32618;
+ cvt.rmi.f32.f32 %f780, %f779;
+ sub.f32 %f781, %f779, %f780;
+ mul.f32 %f782, %f778, 0f3DD2F1AA;
+ cvt.rmi.f32.f32 %f783, %f782;
+ sub.f32 %f784, %f782, %f783;
+ mul.f32 %f785, %f778, 0f3DC74539;
+ cvt.rmi.f32.f32 %f786, %f785;
+ sub.f32 %f787, %f785, %f786;
+ add.f32 %f788, %f784, 0f4199851F;
+ add.f32 %f789, %f787, 0f4199851F;
+ add.f32 %f790, %f781, 0f4199851F;
+ mul.f32 %f791, %f784, %f789;
+ fma.rn.f32 %f792, %f781, %f788, %f791;
+ fma.rn.f32 %f793, %f790, %f787, %f792;
+ add.f32 %f794, %f781, %f793;
+ add.f32 %f795, %f784, %f793;
+ add.f32 %f796, %f787, %f793;
+ add.f32 %f797, %f794, %f795;
+ mul.f32 %f798, %f796, %f797;
+ cvt.rmi.f32.f32 %f799, %f798;
+ sub.f32 %f800, %f798, %f799;
+ add.f32 %f801, %f794, %f796;
+ mul.f32 %f802, %f795, %f801;
+ cvt.rmi.f32.f32 %f803, %f802;
+ sub.f32 %f804, %f802, %f803;
+ add.f32 %f805, %f795, %f796;
+ mul.f32 %f806, %f794, %f805;
+ cvt.rmi.f32.f32 %f807, %f806;
+ sub.f32 %f808, %f806, %f807;
+ fma.rn.f32 %f809, %f800, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f810, %f804, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f811, %f808, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f812, %f347, %f809, %f352;
+ fma.rn.f32 %f813, %f347, %f810, %f353;
+ fma.rn.f32 %f814, %f347, %f811, %f354;
+ sub.f32 %f815, %f812, %f7;
+ sub.f32 %f816, %f813, %f8;
+ sub.f32 %f817, %f814, %f9;
+ mul.f32 %f818, %f816, %f816;
+ fma.rn.f32 %f819, %f815, %f815, %f818;
+ fma.rn.f32 %f820, %f817, %f817, %f819;
+ sqrt.rn.f32 %f675, %f820;
+ rcp.rn.f32 %f821, %f675;
+ mul.f32 %f671, %f821, %f815;
+ mul.f32 %f672, %f821, %f816;
+ mul.f32 %f673, %f821, %f817;
+ ld.global.u32 %r109, [imageEnabled];
+ and.b32 %r110, %r109, 32;
+ setp.eq.s32 %p51, %r110, 0;
+ selp.f32 %f822, 0f3F800000, 0f41200000, %p51;
+ mul.f32 %f674, %f822, %f137;
+ st.local.u32 [%rd2], %r104;
+ ld.global.u32 %r96, [root];
+ // inline asm
+ call _rt_trace_64, (%r96, %f10, %f11, %f12, %f671, %f672, %f673, %r100, %f674, %f675, %rd35, %r28);
+ // inline asm
+ ld.local.f32 %f823, [%rd2];
+ add.f32 %f824, %f777, %f823;
+ add.s32 %r111, %r243, 3;
+ cvt.rn.f32.s32 %f825, %r111;
+ mul.f32 %f826, %f825, 0f3DD32618;
+ cvt.rmi.f32.f32 %f827, %f826;
+ sub.f32 %f828, %f826, %f827;
+ mul.f32 %f829, %f825, 0f3DD2F1AA;
+ cvt.rmi.f32.f32 %f830, %f829;
+ sub.f32 %f831, %f829, %f830;
+ mul.f32 %f832, %f825, 0f3DC74539;
+ cvt.rmi.f32.f32 %f833, %f832;
+ sub.f32 %f834, %f832, %f833;
+ add.f32 %f835, %f831, 0f4199851F;
+ add.f32 %f836, %f834, 0f4199851F;
+ add.f32 %f837, %f828, 0f4199851F;
+ mul.f32 %f838, %f831, %f836;
+ fma.rn.f32 %f839, %f828, %f835, %f838;
+ fma.rn.f32 %f840, %f837, %f834, %f839;
+ add.f32 %f841, %f828, %f840;
+ add.f32 %f842, %f831, %f840;
+ add.f32 %f843, %f834, %f840;
+ add.f32 %f844, %f841, %f842;
+ mul.f32 %f845, %f843, %f844;
+ cvt.rmi.f32.f32 %f846, %f845;
+ sub.f32 %f847, %f845, %f846;
+ add.f32 %f848, %f841, %f843;
+ mul.f32 %f849, %f842, %f848;
+ cvt.rmi.f32.f32 %f850, %f849;
+ sub.f32 %f851, %f849, %f850;
+ add.f32 %f852, %f842, %f843;
+ mul.f32 %f853, %f841, %f852;
+ cvt.rmi.f32.f32 %f854, %f853;
+ sub.f32 %f855, %f853, %f854;
+ fma.rn.f32 %f856, %f847, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f857, %f851, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f858, %f855, 0f40000000, 0fBF800000;
+ fma.rn.f32 %f859, %f347, %f856, %f352;
+ fma.rn.f32 %f860, %f347, %f857, %f353;
+ fma.rn.f32 %f861, %f347, %f858, %f354;
+ sub.f32 %f862, %f859, %f7;
+ sub.f32 %f863, %f860, %f8;
+ sub.f32 %f864, %f861, %f9;
+ mul.f32 %f865, %f863, %f863;
+ fma.rn.f32 %f866, %f862, %f862, %f865;
+ fma.rn.f32 %f867, %f864, %f864, %f866;
+ sqrt.rn.f32 %f683, %f867;
+ rcp.rn.f32 %f868, %f683;
+ mul.f32 %f679, %f868, %f862;
+ mul.f32 %f680, %f868, %f863;
+ mul.f32 %f681, %f868, %f864;
+ ld.global.u32 %r112, [imageEnabled];
+ and.b32 %r113, %r112, 32;
+ setp.eq.s32 %p52, %r113, 0;
+ selp.f32 %f869, 0f3F800000, 0f41200000, %p52;
+ mul.f32 %f682, %f869, %f137;
+ st.local.u32 [%rd2], %r104;
+ ld.global.u32 %r99, [root];
+ // inline asm
+ call _rt_trace_64, (%r99, %f10, %f11, %f12, %f679, %f680, %f681, %r100, %f682, %f683, %rd35, %r28);
+ // inline asm
+ ld.local.f32 %f870, [%rd2];
+ add.f32 %f1345, %f824, %f870;
+ add.s32 %r243, %r243, 4;
+ setp.lt.s32 %p53, %r243, %r6;
+ @%p53 bra BB0_36;
+
+BB0_37:
+ cvt.rn.f32.s32 %f871, %r6;
+ div.rn.f32 %f1346, %f1345, %f871;
+
+BB0_38:
+ fma.rn.f32 %f1318, %f1326, %f1346, %f1318;
+ fma.rn.f32 %f1317, %f1327, %f1346, %f1317;
+ fma.rn.f32 %f1316, %f1328, %f1346, %f1316;
+ fma.rn.f32 %f1315, %f1329, %f1346, %f1315;
+ fma.rn.f32 %f1314, %f1330, %f1346, %f1314;
+ fma.rn.f32 %f1313, %f1331, %f1346, %f1313;
+ fma.rn.f32 %f1312, %f1332, %f1346, %f1312;
+ fma.rn.f32 %f1311, %f1333, %f1346, %f1311;
+ fma.rn.f32 %f1310, %f1334, %f1346, %f1310;
+ fma.rn.f32 %f1309, %f1335, %f1346, %f1309;
+ fma.rn.f32 %f1308, %f1336, %f1346, %f1308;
+ fma.rn.f32 %f1307, %f1337, %f1346, %f1307;
+ fma.rn.f32 %f1306, %f1338, %f1346, %f1306;
+ fma.rn.f32 %f1305, %f1339, %f1346, %f1305;
+ fma.rn.f32 %f1304, %f1340, %f1346, %f1304;
+ add.f32 %f1303, %f1303, %f1346;
+
+BB0_39:
+ add.s32 %r239, %r239, 1;
+ setp.lt.u32 %p54, %r239, %r4;
+ @%p54 bra BB0_5;
+
+BB0_40:
+ ld.global.u32 %r245, [imageEnabled];
+ and.b32 %r114, %r245, 8;
+ setp.eq.s32 %p55, %r114, 0;
+ @%p55 bra BB0_53;
+
+ cvt.sat.f32.f32 %f197, %f1303;
+ cvt.u64.u32 %rd46, %r3;
+ cvt.u64.u32 %rd45, %r2;
+ mov.u64 %rd49, image_Mask;
+ cvta.global.u64 %rd44, %rd49;
+ // inline asm
+ call (%rd43), _rt_buffer_get_64, (%rd44, %r27, %r27, %rd45, %rd46, %rd13, %rd13);
+ // inline asm
+ mov.f32 %f874, 0f3E68BA2E;
+ cvt.rzi.f32.f32 %f875, %f874;
+ fma.rn.f32 %f876, %f875, 0fC0000000, 0f3EE8BA2E;
+ abs.f32 %f198, %f876;
+ abs.f32 %f199, %f197;
+ setp.lt.f32 %p56, %f199, 0f00800000;
+ mul.f32 %f877, %f199, 0f4B800000;
+ selp.f32 %f878, 0fC3170000, 0fC2FE0000, %p56;
+ selp.f32 %f879, %f877, %f199, %p56;
+ mov.b32 %r117, %f879;
+ and.b32 %r118, %r117, 8388607;
+ or.b32 %r119, %r118, 1065353216;
+ mov.b32 %f880, %r119;
+ shr.u32 %r120, %r117, 23;
+ cvt.rn.f32.u32 %f881, %r120;
+ add.f32 %f882, %f878, %f881;
+ setp.gt.f32 %p57, %f880, 0f3FB504F3;
+ mul.f32 %f883, %f880, 0f3F000000;
+ add.f32 %f884, %f882, 0f3F800000;
+ selp.f32 %f885, %f883, %f880, %p57;
+ selp.f32 %f886, %f884, %f882, %p57;
+ add.f32 %f887, %f885, 0fBF800000;
+ add.f32 %f873, %f885, 0f3F800000;
+ // inline asm
+ rcp.approx.ftz.f32 %f872,%f873;
+ // inline asm
+ add.f32 %f888, %f887, %f887;
+ mul.f32 %f889, %f872, %f888;
+ mul.f32 %f890, %f889, %f889;
+ mov.f32 %f891, 0f3C4CAF63;
+ mov.f32 %f892, 0f3B18F0FE;
+ fma.rn.f32 %f893, %f892, %f890, %f891;
+ mov.f32 %f894, 0f3DAAAABD;
+ fma.rn.f32 %f895, %f893, %f890, %f894;
+ mul.rn.f32 %f896, %f895, %f890;
+ mul.rn.f32 %f897, %f896, %f889;
+ sub.f32 %f898, %f887, %f889;
+ neg.f32 %f899, %f889;
+ add.f32 %f900, %f898, %f898;
+ fma.rn.f32 %f901, %f899, %f887, %f900;
+ mul.rn.f32 %f902, %f872, %f901;
+ add.f32 %f903, %f897, %f889;
+ sub.f32 %f904, %f889, %f903;
+ add.f32 %f905, %f897, %f904;
+ add.f32 %f906, %f902, %f905;
+ add.f32 %f907, %f903, %f906;
+ sub.f32 %f908, %f903, %f907;
+ add.f32 %f909, %f906, %f908;
+ mov.f32 %f910, 0f3F317200;
+ mul.rn.f32 %f911, %f886, %f910;
+ mov.f32 %f912, 0f35BFBE8E;
+ mul.rn.f32 %f913, %f886, %f912;
+ add.f32 %f914, %f911, %f907;
+ sub.f32 %f915, %f911, %f914;
+ add.f32 %f916, %f907, %f915;
+ add.f32 %f917, %f909, %f916;
+ add.f32 %f918, %f913, %f917;
+ add.f32 %f919, %f914, %f918;
+ sub.f32 %f920, %f914, %f919;
+ add.f32 %f921, %f918, %f920;
+ mov.f32 %f922, 0f3EE8BA2E;
+ mul.rn.f32 %f923, %f922, %f919;
+ neg.f32 %f924, %f923;
+ fma.rn.f32 %f925, %f922, %f919, %f924;
+ fma.rn.f32 %f926, %f922, %f921, %f925;
+ mov.f32 %f927, 0f00000000;
+ fma.rn.f32 %f928, %f927, %f919, %f926;
+ add.rn.f32 %f929, %f923, %f928;
+ neg.f32 %f930, %f929;
+ add.rn.f32 %f931, %f923, %f930;
+ add.rn.f32 %f932, %f931, %f928;
+ mov.b32 %r121, %f929;
+ setp.eq.s32 %p58, %r121, 1118925336;
+ add.s32 %r122, %r121, -1;
+ mov.b32 %f933, %r122;
+ add.f32 %f934, %f932, 0f37000000;
+ selp.f32 %f935, %f933, %f929, %p58;
+ selp.f32 %f200, %f934, %f932, %p58;
+ mul.f32 %f936, %f935, 0f3FB8AA3B;
+ cvt.rzi.f32.f32 %f937, %f936;
+ mov.f32 %f938, 0fBF317200;
+ fma.rn.f32 %f939, %f937, %f938, %f935;
+ mov.f32 %f940, 0fB5BFBE8E;
+ fma.rn.f32 %f941, %f937, %f940, %f939;
+ mul.f32 %f942, %f941, 0f3FB8AA3B;
+ ex2.approx.ftz.f32 %f943, %f942;
+ add.f32 %f944, %f937, 0f00000000;
+ ex2.approx.f32 %f945, %f944;
+ mul.f32 %f946, %f943, %f945;
+ setp.lt.f32 %p59, %f935, 0fC2D20000;
+ selp.f32 %f947, 0f00000000, %f946, %p59;
+ setp.gt.f32 %p60, %f935, 0f42D20000;
+ selp.f32 %f1379, 0f7F800000, %f947, %p60;
+ setp.eq.f32 %p61, %f1379, 0f7F800000;
+ @%p61 bra BB0_43;
+
+ fma.rn.f32 %f1379, %f1379, %f200, %f1379;
+
+BB0_43:
+ setp.lt.f32 %p62, %f197, 0f00000000;
+ setp.eq.f32 %p63, %f198, 0f3F800000;
+ and.pred %p4, %p62, %p63;
+ mov.b32 %r123, %f1379;
+ xor.b32 %r124, %r123, -2147483648;
+ mov.b32 %f948, %r124;
+ selp.f32 %f1381, %f948, %f1379, %p4;
+ setp.eq.f32 %p64, %f197, 0f00000000;
+ @%p64 bra BB0_46;
+ bra.uni BB0_44;
+
+BB0_46:
+ add.f32 %f951, %f197, %f197;
+ selp.f32 %f1381, %f951, 0f00000000, %p63;
+ bra.uni BB0_47;
+
+BB0_111:
+ mov.u64 %rd190, image_HDR;
+ cvta.global.u64 %rd185, %rd190;
+ mov.u32 %r210, 8;
+ // inline asm
+ call (%rd184), _rt_buffer_get_64, (%rd185, %r27, %r210, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ mov.f32 %f1271, 0f00000000;
+ // inline asm
+ { cvt.rn.f16.f32 %rs104, %f1271;}
+
+ // inline asm
+ mov.u16 %rs105, 0;
+ st.v4.u16 [%rd184], {%rs104, %rs104, %rs104, %rs105};
+
+BB0_112:
+ ld.global.u32 %r211, [additive];
+ setp.eq.s32 %p131, %r211, 0;
+ @%p131 bra BB0_114;
+
+ mov.u64 %rd203, image_RNM0;
+ cvta.global.u64 %rd192, %rd203;
+ mov.u32 %r215, 8;
+ // inline asm
+ call (%rd191), _rt_buffer_get_64, (%rd192, %r27, %r215, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ ld.v4.u16 {%rs112, %rs113, %rs114, %rs115}, [%rd191];
+ // inline asm
+ { cvt.f32.f16 %f1272, %rs112;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1273, %rs113;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1274, %rs114;}
+
+ // inline asm
+ // inline asm
+ call (%rd197), _rt_buffer_get_64, (%rd192, %r27, %r215, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ add.f32 %f1275, %f1272, 0f00000000;
+ add.f32 %f1276, %f1273, 0f00000000;
+ add.f32 %f1277, %f1274, 0f00000000;
+ // inline asm
+ { cvt.rn.f16.f32 %rs111, %f1277;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs110, %f1276;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs109, %f1275;}
+
+ // inline asm
+ mov.u16 %rs116, 0;
+ st.v4.u16 [%rd197], {%rs109, %rs110, %rs111, %rs116};
+ bra.uni BB0_115;
+
+BB0_114:
+ mov.u64 %rd210, image_RNM0;
+ cvta.global.u64 %rd205, %rd210;
+ mov.u32 %r217, 8;
+ // inline asm
+ call (%rd204), _rt_buffer_get_64, (%rd205, %r27, %r217, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ mov.f32 %f1278, 0f00000000;
+ // inline asm
+ { cvt.rn.f16.f32 %rs117, %f1278;}
+
+ // inline asm
+ mov.u16 %rs118, 0;
+ st.v4.u16 [%rd204], {%rs117, %rs117, %rs117, %rs118};
+
+BB0_115:
+ ld.global.u32 %r218, [additive];
+ setp.eq.s32 %p132, %r218, 0;
+ @%p132 bra BB0_117;
+
+ mov.u64 %rd223, image_RNM1;
+ cvta.global.u64 %rd212, %rd223;
+ mov.u32 %r222, 8;
+ // inline asm
+ call (%rd211), _rt_buffer_get_64, (%rd212, %r27, %r222, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ ld.v4.u16 {%rs125, %rs126, %rs127, %rs128}, [%rd211];
+ // inline asm
+ { cvt.f32.f16 %f1279, %rs125;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1280, %rs126;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1281, %rs127;}
+
+ // inline asm
+ // inline asm
+ call (%rd217), _rt_buffer_get_64, (%rd212, %r27, %r222, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ add.f32 %f1282, %f1279, 0f00000000;
+ add.f32 %f1283, %f1280, 0f00000000;
+ add.f32 %f1284, %f1281, 0f00000000;
+ // inline asm
+ { cvt.rn.f16.f32 %rs124, %f1284;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs123, %f1283;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs122, %f1282;}
+
+ // inline asm
+ mov.u16 %rs129, 0;
+ st.v4.u16 [%rd217], {%rs122, %rs123, %rs124, %rs129};
+ bra.uni BB0_118;
+
+BB0_117:
+ mov.u64 %rd230, image_RNM1;
+ cvta.global.u64 %rd225, %rd230;
+ mov.u32 %r224, 8;
+ // inline asm
+ call (%rd224), _rt_buffer_get_64, (%rd225, %r27, %r224, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ mov.f32 %f1285, 0f00000000;
+ // inline asm
+ { cvt.rn.f16.f32 %rs130, %f1285;}
+
+ // inline asm
+ mov.u16 %rs131, 0;
+ st.v4.u16 [%rd224], {%rs130, %rs130, %rs130, %rs131};
+
+BB0_118:
+ ld.global.u32 %r225, [additive];
+ setp.eq.s32 %p133, %r225, 0;
+ @%p133 bra BB0_120;
+
+ mov.u64 %rd243, image_RNM2;
+ cvta.global.u64 %rd232, %rd243;
+ mov.u32 %r229, 8;
+ // inline asm
+ call (%rd231), _rt_buffer_get_64, (%rd232, %r27, %r229, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ ld.v4.u16 {%rs138, %rs139, %rs140, %rs141}, [%rd231];
+ // inline asm
+ { cvt.f32.f16 %f1286, %rs138;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1287, %rs139;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1288, %rs140;}
+
+ // inline asm
+ // inline asm
+ call (%rd237), _rt_buffer_get_64, (%rd232, %r27, %r229, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ add.f32 %f1289, %f1286, 0f00000000;
+ add.f32 %f1290, %f1287, 0f00000000;
+ add.f32 %f1291, %f1288, 0f00000000;
+ // inline asm
+ { cvt.rn.f16.f32 %rs137, %f1291;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs136, %f1290;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs135, %f1289;}
+
+ // inline asm
+ mov.u16 %rs142, 0;
+ st.v4.u16 [%rd237], {%rs135, %rs136, %rs137, %rs142};
+ bra.uni BB0_121;
+
+BB0_120:
+ mov.u64 %rd250, image_RNM2;
+ cvta.global.u64 %rd245, %rd250;
+ mov.u32 %r231, 8;
+ // inline asm
+ call (%rd244), _rt_buffer_get_64, (%rd245, %r27, %r231, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ mov.f32 %f1292, 0f00000000;
+ // inline asm
+ { cvt.rn.f16.f32 %rs143, %f1292;}
+
+ // inline asm
+ mov.u16 %rs144, 0;
+ st.v4.u16 [%rd244], {%rs143, %rs143, %rs143, %rs144};
+
+BB0_121:
+ ld.global.u32 %r232, [additive];
+ setp.eq.s32 %p134, %r232, 0;
+ @%p134 bra BB0_123;
+
+ mov.u64 %rd263, image_RNM3;
+ cvta.global.u64 %rd252, %rd263;
+ mov.u32 %r236, 8;
+ // inline asm
+ call (%rd251), _rt_buffer_get_64, (%rd252, %r27, %r236, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ ld.v4.u16 {%rs151, %rs152, %rs153, %rs154}, [%rd251];
+ // inline asm
+ { cvt.f32.f16 %f1293, %rs151;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1294, %rs152;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1295, %rs153;}
+
+ // inline asm
+ // inline asm
+ call (%rd257), _rt_buffer_get_64, (%rd252, %r27, %r236, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ add.f32 %f1296, %f1293, 0f00000000;
+ add.f32 %f1297, %f1294, 0f00000000;
+ add.f32 %f1298, %f1295, 0f00000000;
+ // inline asm
+ { cvt.rn.f16.f32 %rs150, %f1298;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs149, %f1297;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs148, %f1296;}
+
+ // inline asm
+ mov.u16 %rs155, 0;
+ st.v4.u16 [%rd257], {%rs148, %rs149, %rs150, %rs155};
+ bra.uni BB0_124;
+
+BB0_123:
+ mov.u64 %rd270, image_RNM3;
+ cvta.global.u64 %rd265, %rd270;
+ mov.u32 %r238, 8;
+ // inline asm
+ call (%rd264), _rt_buffer_get_64, (%rd265, %r27, %r238, %rd6, %rd7, %rd13, %rd13);
+ // inline asm
+ mov.f32 %f1299, 0f00000000;
+ // inline asm
+ { cvt.rn.f16.f32 %rs156, %f1299;}
+
+ // inline asm
+ mov.u16 %rs157, 0;
+ st.v4.u16 [%rd264], {%rs156, %rs156, %rs156, %rs157};
+ bra.uni BB0_124;
+
+BB0_44:
+ setp.geu.f32 %p65, %f197, 0f00000000;
+ @%p65 bra BB0_47;
+
+ cvt.rzi.f32.f32 %f950, %f922;
+ setp.neu.f32 %p66, %f950, 0f3EE8BA2E;
+ selp.f32 %f1381, 0f7FFFFFFF, %f1381, %p66;
+
+BB0_47:
+ add.f32 %f952, %f199, 0f3EE8BA2E;
+ mov.b32 %r125, %f952;
+ setp.lt.s32 %p68, %r125, 2139095040;
+ @%p68 bra BB0_52;
+
+ setp.gtu.f32 %p69, %f199, 0f7F800000;
+ @%p69 bra BB0_51;
+ bra.uni BB0_49;
+
+BB0_51:
+ add.f32 %f1381, %f197, 0f3EE8BA2E;
+ bra.uni BB0_52;
+
+BB0_49:
+ setp.neu.f32 %p70, %f199, 0f7F800000;
+ @%p70 bra BB0_52;
+
+ selp.f32 %f1381, 0fFF800000, 0f7F800000, %p4;
+
+BB0_52:
+ mul.f32 %f953, %f1381, 0f437F0000;
+ setp.eq.f32 %p71, %f197, 0f3F800000;
+ selp.f32 %f954, 0f437F0000, %f953, %p71;
+ cvt.rzi.u32.f32 %r126, %f954;
+ cvt.u16.u32 %rs14, %r126;
+ mov.u16 %rs15, 255;
+ st.v2.u8 [%rd43], {%rs14, %rs15};
+ ld.global.u32 %r245, [imageEnabled];
+
+BB0_53:
+ and.b32 %r127, %r245, 1;
+ setp.eq.b32 %p72, %r127, 1;
+ @!%p72 bra BB0_88;
+ bra.uni BB0_54;
+
+BB0_54:
+ mov.f32 %f957, 0f3E666666;
+ cvt.rzi.f32.f32 %f958, %f957;
+ fma.rn.f32 %f959, %f958, 0fC0000000, 0f3EE66666;
+ abs.f32 %f211, %f959;
+ abs.f32 %f212, %f1318;
+ setp.lt.f32 %p73, %f212, 0f00800000;
+ mul.f32 %f960, %f212, 0f4B800000;
+ selp.f32 %f961, 0fC3170000, 0fC2FE0000, %p73;
+ selp.f32 %f962, %f960, %f212, %p73;
+ mov.b32 %r128, %f962;
+ and.b32 %r129, %r128, 8388607;
+ or.b32 %r130, %r129, 1065353216;
+ mov.b32 %f963, %r130;
+ shr.u32 %r131, %r128, 23;
+ cvt.rn.f32.u32 %f964, %r131;
+ add.f32 %f965, %f961, %f964;
+ setp.gt.f32 %p74, %f963, 0f3FB504F3;
+ mul.f32 %f966, %f963, 0f3F000000;
+ add.f32 %f967, %f965, 0f3F800000;
+ selp.f32 %f968, %f966, %f963, %p74;
+ selp.f32 %f969, %f967, %f965, %p74;
+ add.f32 %f970, %f968, 0fBF800000;
+ add.f32 %f956, %f968, 0f3F800000;
+ // inline asm
+ rcp.approx.ftz.f32 %f955,%f956;
+ // inline asm
+ add.f32 %f971, %f970, %f970;
+ mul.f32 %f972, %f955, %f971;
+ mul.f32 %f973, %f972, %f972;
+ mov.f32 %f974, 0f3C4CAF63;
+ mov.f32 %f975, 0f3B18F0FE;
+ fma.rn.f32 %f976, %f975, %f973, %f974;
+ mov.f32 %f977, 0f3DAAAABD;
+ fma.rn.f32 %f978, %f976, %f973, %f977;
+ mul.rn.f32 %f979, %f978, %f973;
+ mul.rn.f32 %f980, %f979, %f972;
+ sub.f32 %f981, %f970, %f972;
+ neg.f32 %f982, %f972;
+ add.f32 %f983, %f981, %f981;
+ fma.rn.f32 %f984, %f982, %f970, %f983;
+ mul.rn.f32 %f985, %f955, %f984;
+ add.f32 %f986, %f980, %f972;
+ sub.f32 %f987, %f972, %f986;
+ add.f32 %f988, %f980, %f987;
+ add.f32 %f989, %f985, %f988;
+ add.f32 %f990, %f986, %f989;
+ sub.f32 %f991, %f986, %f990;
+ add.f32 %f992, %f989, %f991;
+ mov.f32 %f993, 0f3F317200;
+ mul.rn.f32 %f994, %f969, %f993;
+ mov.f32 %f995, 0f35BFBE8E;
+ mul.rn.f32 %f996, %f969, %f995;
+ add.f32 %f997, %f994, %f990;
+ sub.f32 %f998, %f994, %f997;
+ add.f32 %f999, %f990, %f998;
+ add.f32 %f1000, %f992, %f999;
+ add.f32 %f1001, %f996, %f1000;
+ add.f32 %f1002, %f997, %f1001;
+ sub.f32 %f1003, %f997, %f1002;
+ add.f32 %f1004, %f1001, %f1003;
+ mov.f32 %f1005, 0f3EE66666;
+ mul.rn.f32 %f1006, %f1005, %f1002;
+ neg.f32 %f1007, %f1006;
+ fma.rn.f32 %f1008, %f1005, %f1002, %f1007;
+ fma.rn.f32 %f1009, %f1005, %f1004, %f1008;
+ mov.f32 %f1010, 0f00000000;
+ fma.rn.f32 %f1011, %f1010, %f1002, %f1009;
+ add.rn.f32 %f1012, %f1006, %f1011;
+ neg.f32 %f1013, %f1012;
+ add.rn.f32 %f1014, %f1006, %f1013;
+ add.rn.f32 %f1015, %f1014, %f1011;
+ mov.b32 %r132, %f1012;
+ setp.eq.s32 %p75, %r132, 1118925336;
+ add.s32 %r133, %r132, -1;
+ mov.b32 %f1016, %r133;
+ add.f32 %f1017, %f1015, 0f37000000;
+ selp.f32 %f1018, %f1016, %f1012, %p75;
+ selp.f32 %f213, %f1017, %f1015, %p75;
+ mul.f32 %f1019, %f1018, 0f3FB8AA3B;
+ cvt.rzi.f32.f32 %f1020, %f1019;
+ mov.f32 %f1021, 0fBF317200;
+ fma.rn.f32 %f1022, %f1020, %f1021, %f1018;
+ mov.f32 %f1023, 0fB5BFBE8E;
+ fma.rn.f32 %f1024, %f1020, %f1023, %f1022;
+ mul.f32 %f1025, %f1024, 0f3FB8AA3B;
+ ex2.approx.ftz.f32 %f1026, %f1025;
+ add.f32 %f1027, %f1020, 0f00000000;
+ ex2.approx.f32 %f1028, %f1027;
+ mul.f32 %f1029, %f1026, %f1028;
+ setp.lt.f32 %p76, %f1018, 0fC2D20000;
+ selp.f32 %f1030, 0f00000000, %f1029, %p76;
+ setp.gt.f32 %p77, %f1018, 0f42D20000;
+ selp.f32 %f1382, 0f7F800000, %f1030, %p77;
+ setp.eq.f32 %p78, %f1382, 0f7F800000;
+ @%p78 bra BB0_56;
+
+ fma.rn.f32 %f1382, %f1382, %f213, %f1382;
+
+BB0_56:
+ setp.lt.f32 %p79, %f1318, 0f00000000;
+ setp.eq.f32 %p80, %f211, 0f3F800000;
+ and.pred %p5, %p79, %p80;
+ mov.b32 %r134, %f1382;
+ xor.b32 %r135, %r134, -2147483648;
+ mov.b32 %f1031, %r135;
+ selp.f32 %f1384, %f1031, %f1382, %p5;
+ setp.eq.f32 %p81, %f1318, 0f00000000;
+ @%p81 bra BB0_59;
+ bra.uni BB0_57;
+
+BB0_59:
+ add.f32 %f1034, %f1318, %f1318;
+ selp.f32 %f1384, %f1034, 0f00000000, %p80;
+ bra.uni BB0_60;
+
+BB0_57:
+ setp.geu.f32 %p82, %f1318, 0f00000000;
+ @%p82 bra BB0_60;
+
+ cvt.rzi.f32.f32 %f1033, %f1005;
+ setp.neu.f32 %p83, %f1033, 0f3EE66666;
+ selp.f32 %f1384, 0f7FFFFFFF, %f1384, %p83;
+
+BB0_60:
+ add.f32 %f1035, %f212, 0f3EE66666;
+ mov.b32 %r136, %f1035;
+ setp.lt.s32 %p85, %r136, 2139095040;
+ @%p85 bra BB0_65;
+
+ setp.gtu.f32 %p86, %f212, 0f7F800000;
+ @%p86 bra BB0_64;
+ bra.uni BB0_62;
+
+BB0_64:
+ add.f32 %f1384, %f1318, 0f3EE66666;
+ bra.uni BB0_65;
+
+BB0_62:
+ setp.neu.f32 %p87, %f212, 0f7F800000;
+ @%p87 bra BB0_65;
+
+ selp.f32 %f1384, 0fFF800000, 0f7F800000, %p5;
+
+BB0_65:
+ setp.eq.f32 %p88, %f1318, 0f3F800000;
+ selp.f32 %f224, 0f3F800000, %f1384, %p88;
+ abs.f32 %f225, %f1317;
+ setp.lt.f32 %p89, %f225, 0f00800000;
+ mul.f32 %f1038, %f225, 0f4B800000;
+ selp.f32 %f1039, 0fC3170000, 0fC2FE0000, %p89;
+ selp.f32 %f1040, %f1038, %f225, %p89;
+ mov.b32 %r137, %f1040;
+ and.b32 %r138, %r137, 8388607;
+ or.b32 %r139, %r138, 1065353216;
+ mov.b32 %f1041, %r139;
+ shr.u32 %r140, %r137, 23;
+ cvt.rn.f32.u32 %f1042, %r140;
+ add.f32 %f1043, %f1039, %f1042;
+ setp.gt.f32 %p90, %f1041, 0f3FB504F3;
+ mul.f32 %f1044, %f1041, 0f3F000000;
+ add.f32 %f1045, %f1043, 0f3F800000;
+ selp.f32 %f1046, %f1044, %f1041, %p90;
+ selp.f32 %f1047, %f1045, %f1043, %p90;
+ add.f32 %f1048, %f1046, 0fBF800000;
+ add.f32 %f1037, %f1046, 0f3F800000;
+ // inline asm
+ rcp.approx.ftz.f32 %f1036,%f1037;
+ // inline asm
+ add.f32 %f1049, %f1048, %f1048;
+ mul.f32 %f1050, %f1036, %f1049;
+ mul.f32 %f1051, %f1050, %f1050;
+ fma.rn.f32 %f1054, %f975, %f1051, %f974;
+ fma.rn.f32 %f1056, %f1054, %f1051, %f977;
+ mul.rn.f32 %f1057, %f1056, %f1051;
+ mul.rn.f32 %f1058, %f1057, %f1050;
+ sub.f32 %f1059, %f1048, %f1050;
+ neg.f32 %f1060, %f1050;
+ add.f32 %f1061, %f1059, %f1059;
+ fma.rn.f32 %f1062, %f1060, %f1048, %f1061;
+ mul.rn.f32 %f1063, %f1036, %f1062;
+ add.f32 %f1064, %f1058, %f1050;
+ sub.f32 %f1065, %f1050, %f1064;
+ add.f32 %f1066, %f1058, %f1065;
+ add.f32 %f1067, %f1063, %f1066;
+ add.f32 %f1068, %f1064, %f1067;
+ sub.f32 %f1069, %f1064, %f1068;
+ add.f32 %f1070, %f1067, %f1069;
+ mul.rn.f32 %f1072, %f1047, %f993;
+ mul.rn.f32 %f1074, %f1047, %f995;
+ add.f32 %f1075, %f1072, %f1068;
+ sub.f32 %f1076, %f1072, %f1075;
+ add.f32 %f1077, %f1068, %f1076;
+ add.f32 %f1078, %f1070, %f1077;
+ add.f32 %f1079, %f1074, %f1078;
+ add.f32 %f1080, %f1075, %f1079;
+ sub.f32 %f1081, %f1075, %f1080;
+ add.f32 %f1082, %f1079, %f1081;
+ mul.rn.f32 %f1084, %f1005, %f1080;
+ neg.f32 %f1085, %f1084;
+ fma.rn.f32 %f1086, %f1005, %f1080, %f1085;
+ fma.rn.f32 %f1087, %f1005, %f1082, %f1086;
+ fma.rn.f32 %f1089, %f1010, %f1080, %f1087;
+ add.rn.f32 %f1090, %f1084, %f1089;
+ neg.f32 %f1091, %f1090;
+ add.rn.f32 %f1092, %f1084, %f1091;
+ add.rn.f32 %f1093, %f1092, %f1089;
+ mov.b32 %r141, %f1090;
+ setp.eq.s32 %p91, %r141, 1118925336;
+ add.s32 %r142, %r141, -1;
+ mov.b32 %f1094, %r142;
+ add.f32 %f1095, %f1093, 0f37000000;
+ selp.f32 %f1096, %f1094, %f1090, %p91;
+ selp.f32 %f226, %f1095, %f1093, %p91;
+ mul.f32 %f1097, %f1096, 0f3FB8AA3B;
+ cvt.rzi.f32.f32 %f1098, %f1097;
+ fma.rn.f32 %f1100, %f1098, %f1021, %f1096;
+ fma.rn.f32 %f1102, %f1098, %f1023, %f1100;
+ mul.f32 %f1103, %f1102, 0f3FB8AA3B;
+ ex2.approx.ftz.f32 %f1104, %f1103;
+ add.f32 %f1105, %f1098, 0f00000000;
+ ex2.approx.f32 %f1106, %f1105;
+ mul.f32 %f1107, %f1104, %f1106;
+ setp.lt.f32 %p92, %f1096, 0fC2D20000;
+ selp.f32 %f1108, 0f00000000, %f1107, %p92;
+ setp.gt.f32 %p93, %f1096, 0f42D20000;
+ selp.f32 %f1385, 0f7F800000, %f1108, %p93;
+ setp.eq.f32 %p94, %f1385, 0f7F800000;
+ @%p94 bra BB0_67;
+
+ fma.rn.f32 %f1385, %f1385, %f226, %f1385;
+
+BB0_67:
+ setp.lt.f32 %p95, %f1317, 0f00000000;
+ and.pred %p6, %p95, %p80;
+ mov.b32 %r143, %f1385;
+ xor.b32 %r144, %r143, -2147483648;
+ mov.b32 %f1109, %r144;
+ selp.f32 %f1387, %f1109, %f1385, %p6;
+ setp.eq.f32 %p97, %f1317, 0f00000000;
+ @%p97 bra BB0_70;
+ bra.uni BB0_68;
+
+BB0_70:
+ add.f32 %f1112, %f1317, %f1317;
+ selp.f32 %f1387, %f1112, 0f00000000, %p80;
+ bra.uni BB0_71;
+
+BB0_68:
+ setp.geu.f32 %p98, %f1317, 0f00000000;
+ @%p98 bra BB0_71;
+
+ cvt.rzi.f32.f32 %f1111, %f1005;
+ setp.neu.f32 %p99, %f1111, 0f3EE66666;
+ selp.f32 %f1387, 0f7FFFFFFF, %f1387, %p99;
+
+BB0_71:
+ add.f32 %f1113, %f225, 0f3EE66666;
+ mov.b32 %r145, %f1113;
+ setp.lt.s32 %p101, %r145, 2139095040;
+ @%p101 bra BB0_76;
+
+ setp.gtu.f32 %p102, %f225, 0f7F800000;
+ @%p102 bra BB0_75;
+ bra.uni BB0_73;
+
+BB0_75:
+ add.f32 %f1387, %f1317, 0f3EE66666;
+ bra.uni BB0_76;
+
+BB0_73:
+ setp.neu.f32 %p103, %f225, 0f7F800000;
+ @%p103 bra BB0_76;
+
+ selp.f32 %f1387, 0fFF800000, 0f7F800000, %p6;
+
+BB0_76:
+ setp.eq.f32 %p104, %f1317, 0f3F800000;
+ selp.f32 %f237, 0f3F800000, %f1387, %p104;
+ abs.f32 %f238, %f1316;
+ setp.lt.f32 %p105, %f238, 0f00800000;
+ mul.f32 %f1116, %f238, 0f4B800000;
+ selp.f32 %f1117, 0fC3170000, 0fC2FE0000, %p105;
+ selp.f32 %f1118, %f1116, %f238, %p105;
+ mov.b32 %r146, %f1118;
+ and.b32 %r147, %r146, 8388607;
+ or.b32 %r148, %r147, 1065353216;
+ mov.b32 %f1119, %r148;
+ shr.u32 %r149, %r146, 23;
+ cvt.rn.f32.u32 %f1120, %r149;
+ add.f32 %f1121, %f1117, %f1120;
+ setp.gt.f32 %p106, %f1119, 0f3FB504F3;
+ mul.f32 %f1122, %f1119, 0f3F000000;
+ add.f32 %f1123, %f1121, 0f3F800000;
+ selp.f32 %f1124, %f1122, %f1119, %p106;
+ selp.f32 %f1125, %f1123, %f1121, %p106;
+ add.f32 %f1126, %f1124, 0fBF800000;
+ add.f32 %f1115, %f1124, 0f3F800000;
+ // inline asm
+ rcp.approx.ftz.f32 %f1114,%f1115;
+ // inline asm
+ add.f32 %f1127, %f1126, %f1126;
+ mul.f32 %f1128, %f1114, %f1127;
+ mul.f32 %f1129, %f1128, %f1128;
+ fma.rn.f32 %f1132, %f975, %f1129, %f974;
+ fma.rn.f32 %f1134, %f1132, %f1129, %f977;
+ mul.rn.f32 %f1135, %f1134, %f1129;
+ mul.rn.f32 %f1136, %f1135, %f1128;
+ sub.f32 %f1137, %f1126, %f1128;
+ neg.f32 %f1138, %f1128;
+ add.f32 %f1139, %f1137, %f1137;
+ fma.rn.f32 %f1140, %f1138, %f1126, %f1139;
+ mul.rn.f32 %f1141, %f1114, %f1140;
+ add.f32 %f1142, %f1136, %f1128;
+ sub.f32 %f1143, %f1128, %f1142;
+ add.f32 %f1144, %f1136, %f1143;
+ add.f32 %f1145, %f1141, %f1144;
+ add.f32 %f1146, %f1142, %f1145;
+ sub.f32 %f1147, %f1142, %f1146;
+ add.f32 %f1148, %f1145, %f1147;
+ mul.rn.f32 %f1150, %f1125, %f993;
+ mul.rn.f32 %f1152, %f1125, %f995;
+ add.f32 %f1153, %f1150, %f1146;
+ sub.f32 %f1154, %f1150, %f1153;
+ add.f32 %f1155, %f1146, %f1154;
+ add.f32 %f1156, %f1148, %f1155;
+ add.f32 %f1157, %f1152, %f1156;
+ add.f32 %f1158, %f1153, %f1157;
+ sub.f32 %f1159, %f1153, %f1158;
+ add.f32 %f1160, %f1157, %f1159;
+ mul.rn.f32 %f1162, %f1005, %f1158;
+ neg.f32 %f1163, %f1162;
+ fma.rn.f32 %f1164, %f1005, %f1158, %f1163;
+ fma.rn.f32 %f1165, %f1005, %f1160, %f1164;
+ fma.rn.f32 %f1167, %f1010, %f1158, %f1165;
+ add.rn.f32 %f1168, %f1162, %f1167;
+ neg.f32 %f1169, %f1168;
+ add.rn.f32 %f1170, %f1162, %f1169;
+ add.rn.f32 %f1171, %f1170, %f1167;
+ mov.b32 %r150, %f1168;
+ setp.eq.s32 %p107, %r150, 1118925336;
+ add.s32 %r151, %r150, -1;
+ mov.b32 %f1172, %r151;
+ add.f32 %f1173, %f1171, 0f37000000;
+ selp.f32 %f1174, %f1172, %f1168, %p107;
+ selp.f32 %f239, %f1173, %f1171, %p107;
+ mul.f32 %f1175, %f1174, 0f3FB8AA3B;
+ cvt.rzi.f32.f32 %f1176, %f1175;
+ fma.rn.f32 %f1178, %f1176, %f1021, %f1174;
+ fma.rn.f32 %f1180, %f1176, %f1023, %f1178;
+ mul.f32 %f1181, %f1180, 0f3FB8AA3B;
+ ex2.approx.ftz.f32 %f1182, %f1181;
+ add.f32 %f1183, %f1176, 0f00000000;
+ ex2.approx.f32 %f1184, %f1183;
+ mul.f32 %f1185, %f1182, %f1184;
+ setp.lt.f32 %p108, %f1174, 0fC2D20000;
+ selp.f32 %f1186, 0f00000000, %f1185, %p108;
+ setp.gt.f32 %p109, %f1174, 0f42D20000;
+ selp.f32 %f1388, 0f7F800000, %f1186, %p109;
+ setp.eq.f32 %p110, %f1388, 0f7F800000;
+ @%p110 bra BB0_78;
+
+ fma.rn.f32 %f1388, %f1388, %f239, %f1388;
+
+BB0_78:
+ setp.lt.f32 %p111, %f1316, 0f00000000;
+ and.pred %p7, %p111, %p80;
+ mov.b32 %r152, %f1388;
+ xor.b32 %r153, %r152, -2147483648;
+ mov.b32 %f1187, %r153;
+ selp.f32 %f1390, %f1187, %f1388, %p7;
+ setp.eq.f32 %p113, %f1316, 0f00000000;
+ @%p113 bra BB0_81;
+ bra.uni BB0_79;
+
+BB0_81:
+ add.f32 %f1190, %f1316, %f1316;
+ selp.f32 %f1390, %f1190, 0f00000000, %p80;
+ bra.uni BB0_82;
+
+BB0_79:
+ setp.geu.f32 %p114, %f1316, 0f00000000;
+ @%p114 bra BB0_82;
+
+ cvt.rzi.f32.f32 %f1189, %f1005;
+ setp.neu.f32 %p115, %f1189, 0f3EE66666;
+ selp.f32 %f1390, 0f7FFFFFFF, %f1390, %p115;
+
+BB0_82:
+ add.f32 %f1191, %f238, 0f3EE66666;
+ mov.b32 %r154, %f1191;
+ setp.lt.s32 %p117, %r154, 2139095040;
+ @%p117 bra BB0_87;
+
+ setp.gtu.f32 %p118, %f238, 0f7F800000;
+ @%p118 bra BB0_86;
+ bra.uni BB0_84;
+
+BB0_86:
+ add.f32 %f1390, %f1316, 0f3EE66666;
+ bra.uni BB0_87;
+
+BB0_84:
+ setp.neu.f32 %p119, %f238, 0f7F800000;
+ @%p119 bra BB0_87;
+
+ selp.f32 %f1390, 0fFF800000, 0f7F800000, %p7;
+
+BB0_87:
+ setp.eq.f32 %p120, %f1316, 0f3F800000;
+ selp.f32 %f1192, 0f3F800000, %f1390, %p120;
+ cvt.u64.u32 %rd53, %r3;
+ cvt.u64.u32 %rd52, %r2;
+ mov.u64 %rd56, image;
+ cvta.global.u64 %rd51, %rd56;
+ // inline asm
+ call (%rd50), _rt_buffer_get_64, (%rd51, %r27, %r28, %rd52, %rd53, %rd13, %rd13);
+ // inline asm
+ cvt.sat.f32.f32 %f1193, %f1192;
+ mul.f32 %f1194, %f1193, 0f437FFD71;
+ cvt.rzi.u32.f32 %r157, %f1194;
+ cvt.sat.f32.f32 %f1195, %f237;
+ mul.f32 %f1196, %f1195, 0f437FFD71;
+ cvt.rzi.u32.f32 %r158, %f1196;
+ cvt.sat.f32.f32 %f1197, %f224;
+ mul.f32 %f1198, %f1197, 0f437FFD71;
+ cvt.rzi.u32.f32 %r159, %f1198;
+ cvt.u16.u32 %rs16, %r157;
+ cvt.u16.u32 %rs17, %r159;
+ cvt.u16.u32 %rs18, %r158;
+ mov.u16 %rs19, 255;
+ st.v4.u8 [%rd50], {%rs16, %rs18, %rs17, %rs19};
+ ld.global.u32 %r245, [imageEnabled];
+
+BB0_88:
+ cvt.u64.u32 %rd4, %r2;
+ cvt.u64.u32 %rd5, %r3;
+ and.b32 %r160, %r245, 4;
+ setp.eq.s32 %p121, %r160, 0;
+ @%p121 bra BB0_92;
+
+ ld.global.u32 %r161, [additive];
+ setp.eq.s32 %p122, %r161, 0;
+ mov.f32 %f1199, 0f3F800000;
+ // inline asm
+ { cvt.rn.f16.f32 %rs20, %f1199;}
+
+ // inline asm
+ @%p122 bra BB0_91;
+
+ mov.u64 %rd69, image_HDR;
+ cvta.global.u64 %rd58, %rd69;
+ mov.u32 %r165, 8;
+ // inline asm
+ call (%rd57), _rt_buffer_get_64, (%rd58, %r27, %r165, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ ld.v4.u16 {%rs27, %rs28, %rs29, %rs30}, [%rd57];
+ // inline asm
+ { cvt.f32.f16 %f1200, %rs27;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1201, %rs28;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1202, %rs29;}
+
+ // inline asm
+ // inline asm
+ call (%rd63), _rt_buffer_get_64, (%rd58, %r27, %r165, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ add.f32 %f1203, %f1318, %f1200;
+ add.f32 %f1204, %f1317, %f1201;
+ add.f32 %f1205, %f1316, %f1202;
+ // inline asm
+ { cvt.rn.f16.f32 %rs26, %f1205;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs25, %f1204;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs24, %f1203;}
+
+ // inline asm
+ st.v4.u16 [%rd63], {%rs24, %rs25, %rs26, %rs20};
+ bra.uni BB0_92;
+
+BB0_91:
+ mov.u64 %rd76, image_HDR;
+ cvta.global.u64 %rd71, %rd76;
+ mov.u32 %r167, 8;
+ // inline asm
+ call (%rd70), _rt_buffer_get_64, (%rd71, %r27, %r167, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs33, %f1316;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs32, %f1317;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs31, %f1318;}
+
+ // inline asm
+ st.v4.u16 [%rd70], {%rs31, %rs32, %rs33, %rs20};
+
+BB0_92:
+ mov.f32 %f1210, 0f34000000;
+ max.f32 %f1211, %f1315, %f1210;
+ div.rn.f32 %f1212, %f1312, %f1211;
+ max.f32 %f1213, %f1314, %f1210;
+ div.rn.f32 %f1214, %f1311, %f1213;
+ max.f32 %f1215, %f1313, %f1210;
+ div.rn.f32 %f1216, %f1310, %f1215;
+ fma.rn.f32 %f250, %f1212, 0f3F000000, 0f3F000000;
+ fma.rn.f32 %f251, %f1214, 0f3F000000, 0f3F000000;
+ fma.rn.f32 %f252, %f1216, 0f3F000000, 0f3F000000;
+ div.rn.f32 %f1217, %f1309, %f1211;
+ div.rn.f32 %f1218, %f1308, %f1213;
+ div.rn.f32 %f1219, %f1307, %f1215;
+ fma.rn.f32 %f253, %f1217, 0f3F000000, 0f3F000000;
+ fma.rn.f32 %f254, %f1218, 0f3F000000, 0f3F000000;
+ fma.rn.f32 %f255, %f1219, 0f3F000000, 0f3F000000;
+ div.rn.f32 %f1220, %f1306, %f1211;
+ div.rn.f32 %f1221, %f1305, %f1213;
+ div.rn.f32 %f1222, %f1304, %f1215;
+ fma.rn.f32 %f256, %f1220, 0f3F000000, 0f3F000000;
+ fma.rn.f32 %f257, %f1221, 0f3F000000, 0f3F000000;
+ fma.rn.f32 %f258, %f1222, 0f3F000000, 0f3F000000;
+ ld.global.u32 %r168, [additive];
+ setp.eq.s32 %p123, %r168, 0;
+ mov.f32 %f1209, 0f3F800000;
+ // inline asm
+ { cvt.rn.f16.f32 %rs34, %f1209;}
+
+ // inline asm
+ @%p123 bra BB0_94;
+
+ mov.u64 %rd89, image_RNM0;
+ cvta.global.u64 %rd78, %rd89;
+ mov.u32 %r172, 8;
+ // inline asm
+ call (%rd77), _rt_buffer_get_64, (%rd78, %r27, %r172, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ ld.v4.u16 {%rs41, %rs42, %rs43, %rs44}, [%rd77];
+ // inline asm
+ { cvt.f32.f16 %f1223, %rs41;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1224, %rs42;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1225, %rs43;}
+
+ // inline asm
+ // inline asm
+ call (%rd83), _rt_buffer_get_64, (%rd78, %r27, %r172, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ add.f32 %f1226, %f1315, %f1223;
+ add.f32 %f1227, %f1314, %f1224;
+ add.f32 %f1228, %f1313, %f1225;
+ // inline asm
+ { cvt.rn.f16.f32 %rs40, %f1228;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs39, %f1227;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs38, %f1226;}
+
+ // inline asm
+ st.v4.u16 [%rd83], {%rs38, %rs39, %rs40, %rs34};
+ bra.uni BB0_95;
+
+BB0_94:
+ mov.u64 %rd96, image_RNM0;
+ cvta.global.u64 %rd91, %rd96;
+ mov.u32 %r174, 8;
+ // inline asm
+ call (%rd90), _rt_buffer_get_64, (%rd91, %r27, %r174, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs47, %f1313;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs46, %f1314;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs45, %f1315;}
+
+ // inline asm
+ st.v4.u16 [%rd90], {%rs45, %rs46, %rs47, %rs34};
+
+BB0_95:
+ ld.global.u32 %r175, [additive];
+ setp.eq.s32 %p124, %r175, 0;
+ // inline asm
+ { cvt.rn.f16.f32 %rs48, %f1209;}
+
+ // inline asm
+ @%p124 bra BB0_97;
+
+ mov.u64 %rd109, image_RNM1;
+ cvta.global.u64 %rd98, %rd109;
+ mov.u32 %r179, 8;
+ // inline asm
+ call (%rd97), _rt_buffer_get_64, (%rd98, %r27, %r179, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ ld.v4.u16 {%rs55, %rs56, %rs57, %rs58}, [%rd97];
+ // inline asm
+ { cvt.f32.f16 %f1233, %rs55;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1234, %rs56;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1235, %rs57;}
+
+ // inline asm
+ // inline asm
+ call (%rd103), _rt_buffer_get_64, (%rd98, %r27, %r179, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ add.f32 %f1236, %f250, %f1233;
+ add.f32 %f1237, %f251, %f1234;
+ add.f32 %f1238, %f252, %f1235;
+ // inline asm
+ { cvt.rn.f16.f32 %rs54, %f1238;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs53, %f1237;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs52, %f1236;}
+
+ // inline asm
+ st.v4.u16 [%rd103], {%rs52, %rs53, %rs54, %rs48};
+ bra.uni BB0_98;
+
+BB0_97:
+ mov.u64 %rd116, image_RNM1;
+ cvta.global.u64 %rd111, %rd116;
+ mov.u32 %r181, 8;
+ // inline asm
+ call (%rd110), _rt_buffer_get_64, (%rd111, %r27, %r181, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs61, %f252;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs60, %f251;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs59, %f250;}
+
+ // inline asm
+ st.v4.u16 [%rd110], {%rs59, %rs60, %rs61, %rs48};
+
+BB0_98:
+ ld.global.u32 %r182, [additive];
+ setp.eq.s32 %p125, %r182, 0;
+ // inline asm
+ { cvt.rn.f16.f32 %rs62, %f1209;}
+
+ // inline asm
+ @%p125 bra BB0_100;
+
+ mov.u64 %rd129, image_RNM2;
+ cvta.global.u64 %rd118, %rd129;
+ mov.u32 %r186, 8;
+ // inline asm
+ call (%rd117), _rt_buffer_get_64, (%rd118, %r27, %r186, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ ld.v4.u16 {%rs69, %rs70, %rs71, %rs72}, [%rd117];
+ // inline asm
+ { cvt.f32.f16 %f1243, %rs69;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1244, %rs70;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1245, %rs71;}
+
+ // inline asm
+ // inline asm
+ call (%rd123), _rt_buffer_get_64, (%rd118, %r27, %r186, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ add.f32 %f1246, %f253, %f1243;
+ add.f32 %f1247, %f254, %f1244;
+ add.f32 %f1248, %f255, %f1245;
+ // inline asm
+ { cvt.rn.f16.f32 %rs68, %f1248;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs67, %f1247;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs66, %f1246;}
+
+ // inline asm
+ st.v4.u16 [%rd123], {%rs66, %rs67, %rs68, %rs62};
+ bra.uni BB0_101;
+
+BB0_100:
+ mov.u64 %rd136, image_RNM2;
+ cvta.global.u64 %rd131, %rd136;
+ mov.u32 %r188, 8;
+ // inline asm
+ call (%rd130), _rt_buffer_get_64, (%rd131, %r27, %r188, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs75, %f255;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs74, %f254;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs73, %f253;}
+
+ // inline asm
+ st.v4.u16 [%rd130], {%rs73, %rs74, %rs75, %rs62};
+
+BB0_101:
+ ld.global.u32 %r189, [additive];
+ setp.eq.s32 %p126, %r189, 0;
+ // inline asm
+ { cvt.rn.f16.f32 %rs76, %f1209;}
+
+ // inline asm
+ @%p126 bra BB0_103;
+
+ mov.u64 %rd149, image_RNM3;
+ cvta.global.u64 %rd138, %rd149;
+ mov.u32 %r193, 8;
+ // inline asm
+ call (%rd137), _rt_buffer_get_64, (%rd138, %r27, %r193, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ ld.v4.u16 {%rs83, %rs84, %rs85, %rs86}, [%rd137];
+ // inline asm
+ { cvt.f32.f16 %f1253, %rs83;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1254, %rs84;}
+
+ // inline asm
+ // inline asm
+ { cvt.f32.f16 %f1255, %rs85;}
+
+ // inline asm
+ // inline asm
+ call (%rd143), _rt_buffer_get_64, (%rd138, %r27, %r193, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ add.f32 %f1256, %f256, %f1253;
+ add.f32 %f1257, %f257, %f1254;
+ add.f32 %f1258, %f258, %f1255;
+ // inline asm
+ { cvt.rn.f16.f32 %rs82, %f1258;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs81, %f1257;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs80, %f1256;}
+
+ // inline asm
+ st.v4.u16 [%rd143], {%rs80, %rs81, %rs82, %rs76};
+ bra.uni BB0_124;
+
+BB0_103:
+ mov.u64 %rd156, image_RNM3;
+ cvta.global.u64 %rd151, %rd156;
+ mov.u32 %r195, 8;
+ // inline asm
+ call (%rd150), _rt_buffer_get_64, (%rd151, %r27, %r195, %rd4, %rd5, %rd13, %rd13);
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs89, %f258;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs88, %f257;}
+
+ // inline asm
+ // inline asm
+ { cvt.rn.f16.f32 %rs87, %f256;}
+
+ // inline asm
+ st.v4.u16 [%rd150], {%rs87, %rs88, %rs89, %rs76};
+
+BB0_124:
+ ret;
+}
+
+
generated by cgit v1.2.3-freya (git 2.51.0) at 2025-10-01 22:46:37 +0000