diff options
Diffstat (limited to 'VRCSDK3Worlds/Assets/Editor/x64/Bakery/denoisePrepareOIDN.ptx')
| -rw-r--r-- | VRCSDK3Worlds/Assets/Editor/x64/Bakery/denoisePrepareOIDN.ptx | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/VRCSDK3Worlds/Assets/Editor/x64/Bakery/denoisePrepareOIDN.ptx b/VRCSDK3Worlds/Assets/Editor/x64/Bakery/denoisePrepareOIDN.ptx new file mode 100644 index 00000000..d2b42d8d --- /dev/null +++ b/VRCSDK3Worlds/Assets/Editor/x64/Bakery/denoisePrepareOIDN.ptx @@ -0,0 +1,116 @@ +// +// Generated by NVIDIA NVVM Compiler +// +// Compiler Build ID: CL-23083092 +// Cuda compilation tools, release 9.1, V9.1.85 +// Based on LLVM 3.4svn +// + +.version 6.1 +.target sm_30 +.address_size 64 + + // .globl _Z6oxMainv +.global .align 8 .b8 pixelID[8]; +.global .align 8 .b8 resolution[8]; +.global .align 1 .b8 image[1]; +.global .align 1 .b8 input_buffer[1]; +.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0}; +.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0}; +.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE; +.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E; +.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E; +.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E; +.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E; +.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E; +.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E; +.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E; +.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E; +.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E; +.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E; +.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E; +.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E; +.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E; +.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E; +.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E; +.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E; +.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E; +.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E; +.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E; +.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E; +.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE; +.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE; +.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE; +.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0}; +.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0}; +.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919; +.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919; +.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0}; +.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0}; +.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1]; +.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1]; + +.visible .entry _Z6oxMainv( + +) +{ + .reg .b16 %rs<4>; + .reg .f32 %f<4>; + .reg .b32 %r<25>; + .reg .b64 %rd<27>; + + + ld.global.v2.u32 {%r9, %r10}, [pixelID]; + cvt.u64.u32 %rd3, %r9; + cvt.u64.u32 %rd4, %r10; + mov.u64 %rd25, image; + cvta.global.u64 %rd2, %rd25; + mov.u32 %r7, 2; + mov.u32 %r6, 8; + mov.u64 %rd24, 0; + // inline asm + call (%rd1), _rt_buffer_get_64, (%rd2, %r7, %r6, %rd3, %rd4, %rd24, %rd24); + // inline asm + ld.u16 %rs1, [%rd1]; + // inline asm + { cvt.f32.f16 %f1, %rs1;} + + // inline asm + ld.global.v2.u32 {%r13, %r14}, [pixelID]; + cvt.u64.u32 %rd9, %r13; + cvt.u64.u32 %rd10, %r14; + // inline asm + call (%rd7), _rt_buffer_get_64, (%rd2, %r7, %r6, %rd9, %rd10, %rd24, %rd24); + // inline asm + ld.u16 %rs2, [%rd7+2]; + // inline asm + { cvt.f32.f16 %f2, %rs2;} + + // inline asm + ld.global.v2.u32 {%r17, %r18}, [pixelID]; + cvt.u64.u32 %rd15, %r17; + cvt.u64.u32 %rd16, %r18; + // inline asm + call (%rd13), _rt_buffer_get_64, (%rd2, %r7, %r6, %rd15, %rd16, %rd24, %rd24); + // inline asm + ld.u16 %rs3, [%rd13+4]; + // inline asm + { cvt.f32.f16 %f3, %rs3;} + + // inline asm + ld.global.v2.u32 {%r21, %r22}, [pixelID]; + cvt.u64.u32 %rd21, %r21; + cvt.u64.u32 %rd22, %r22; + mov.u64 %rd26, input_buffer; + cvta.global.u64 %rd20, %rd26; + mov.u32 %r8, 12; + // inline asm + call (%rd19), _rt_buffer_get_64, (%rd20, %r7, %r8, %rd21, %rd22, %rd24, %rd24); + // inline asm + st.f32 [%rd19+8], %f3; + st.f32 [%rd19+4], %f2; + st.f32 [%rd19], %f1; + ret; +} + + |