move to self host

1 files changed, 2112 insertions, 0 deletions

diff --git a/VRCSDK3Worlds/Assets/Editor/x64/Bakery/lmSunSH.ptx b/VRCSDK3Worlds/Assets/Editor/x64/Bakery/lmSunSH.ptx
new file mode 100644
index 00000000..78397089
--- /dev/null
+++ b/VRCSDK3Worlds/Assets/Editor/x64/Bakery/lmSunSH.ptx
@@ -0,0 +1,2112 @@
+//
+// Generated by NVIDIA NVVM Compiler
+//
+// Compiler Build ID: CL-23083092
+// Cuda compilation tools, release 9.1, V9.1.85
+// Based on LLVM 3.4svn
+//
+
+.version 6.1
+.target sm_30
+.address_size 64
+
+	// .globl	_Z6oxMainv
+.global .align 8 .b8 pixelID[8];
+.global .align 8 .b8 resolution[8];
+.global .align 4 .b8 normal[12];
+.global .align 4 .b8 camPos[12];
+.global .align 4 .b8 root[4];
+.global .align 4 .u32 imageEnabled;
+.global .texref lightmap;
+.global .align 16 .b8 tileInfo[16];
+.global .align 4 .u32 additive;
+.global .align 1 .b8 image[1];
+.global .align 1 .b8 image_HDR[1];
+.global .align 1 .b8 image_HDR2[1];
+.global .align 1 .b8 image_Mask[1];
+.global .align 1 .b8 image_RNM0[1];
+.global .align 1 .b8 image_RNM1[1];
+.global .align 1 .b8 image_RNM2[1];
+.global .align 1 .b8 image_RNM3[1];
+.global .align 1 .b8 uvpos[1];
+.global .align 1 .b8 uvnormal[1];
+.global .align 1 .b8 rnd_seeds[1];
+.global .align 4 .b8 directDir[12];
+.global .align 4 .b8 directColor[12];
+.global .align 4 .f32 shadowSpread;
+.global .align 4 .u32 samples;
+.global .align 4 .u32 ignoreNormal;
+.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo6normalE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo6camPosE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo4rootE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo12imageEnabledE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo8tileInfoE[8] = {82, 97, 121, 0, 16, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo8additiveE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo9directDirE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo11directColorE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo12shadowSpreadE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo7samplesE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo12ignoreNormalE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E;
+.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE;
+.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE;
+.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE;
+.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename6normalE[7] = {102, 108, 111, 97, 116, 51, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename6camPosE[7] = {102, 108, 111, 97, 116, 51, 0};
+.global .align 16 .b8 _ZN21rti_internal_typename4rootE[9] = {114, 116, 79, 98, 106, 101, 99, 116, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename12imageEnabledE[4] = {105, 110, 116, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename8tileInfoE[6] = {117, 105, 110, 116, 52, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename8additiveE[4] = {105, 110, 116, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename9directDirE[7] = {102, 108, 111, 97, 116, 51, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename11directColorE[7] = {102, 108, 111, 97, 116, 51, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename12shadowSpreadE[6] = {102, 108, 111, 97, 116, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename7samplesE[4] = {105, 110, 116, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename12ignoreNormalE[4] = {105, 110, 116, 0};
+.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum6normalE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum6camPosE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum4rootE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum12imageEnabledE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum8tileInfoE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum8additiveE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum9directDirE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum11directColorE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum12shadowSpreadE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum7samplesE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum12ignoreNormalE = 4919;
+.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0};
+.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0};
+.global .align 16 .b8 _ZN21rti_internal_semantic6normalE[17] = {97, 116, 116, 114, 105, 98, 117, 116, 101, 32, 110, 111, 114, 109, 97, 108, 0};
+.global .align 1 .b8 _ZN21rti_internal_semantic6camPosE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic4rootE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic12imageEnabledE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic8tileInfoE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic8additiveE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic9directDirE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic11directColorE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic12shadowSpreadE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic7samplesE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic12ignoreNormalE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation6normalE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation6camPosE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation4rootE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation12imageEnabledE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation8tileInfoE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation8additiveE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation9directDirE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation11directColorE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation12shadowSpreadE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation7samplesE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation12ignoreNormalE[1];
+.const .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
+
+.visible .entry _Z6oxMainv(
+
+)
+{
+	.local .align 4 .b8 	__local_depot0[32];
+	.reg .b64 	%SP;
+	.reg .b64 	%SPL;
+	.reg .pred 	%p<124>;
+	.reg .b16 	%rs<152>;
+	.reg .f32 	%f<796>;
+	.reg .b32 	%r<388>;
+	.reg .b64 	%rd<286>;
+
+
+	mov.u64 	%rd285, __local_depot0;
+	cvta.local.u64 	%SP, %rd285;
+	ld.global.v2.u32 	{%r101, %r102}, [pixelID];
+	cvt.u64.u32	%rd22, %r101;
+	cvt.u64.u32	%rd23, %r102;
+	mov.u64 	%rd26, uvnormal;
+	cvta.global.u64 	%rd21, %rd26;
+	mov.u32 	%r99, 2;
+	mov.u32 	%r100, 4;
+	mov.u64 	%rd25, 0;
+	// inline asm
+	call (%rd20), _rt_buffer_get_64, (%rd21, %r99, %r100, %rd22, %rd23, %rd25, %rd25);
+	// inline asm
+	ld.u32 	%r1, [%rd20];
+	shr.u32 	%r105, %r1, 16;
+	cvt.u16.u32	%rs1, %r105;
+	and.b16  	%rs7, %rs1, 255;
+	cvt.u16.u32	%rs8, %r1;
+	or.b16  	%rs9, %rs8, %rs7;
+	setp.eq.s16	%p5, %rs9, 0;
+	mov.f32 	%f764, 0f00000000;
+	mov.f32 	%f765, %f764;
+	mov.f32 	%f766, %f764;
+	@%p5 bra 	BB0_2;
+
+	ld.u8 	%rs10, [%rd20+1];
+	and.b16  	%rs12, %rs8, 255;
+	cvt.rn.f32.u16	%f134, %rs12;
+	div.rn.f32 	%f135, %f134, 0f437F0000;
+	fma.rn.f32 	%f136, %f135, 0f40000000, 0fBF800000;
+	cvt.rn.f32.u16	%f137, %rs10;
+	div.rn.f32 	%f138, %f137, 0f437F0000;
+	fma.rn.f32 	%f139, %f138, 0f40000000, 0fBF800000;
+	cvt.rn.f32.u16	%f140, %rs7;
+	div.rn.f32 	%f141, %f140, 0f437F0000;
+	fma.rn.f32 	%f142, %f141, 0f40000000, 0fBF800000;
+	mul.f32 	%f143, %f139, %f139;
+	fma.rn.f32 	%f144, %f136, %f136, %f143;
+	fma.rn.f32 	%f145, %f142, %f142, %f144;
+	sqrt.rn.f32 	%f146, %f145;
+	rcp.rn.f32 	%f147, %f146;
+	mul.f32 	%f764, %f136, %f147;
+	mul.f32 	%f765, %f139, %f147;
+	mul.f32 	%f766, %f142, %f147;
+
+BB0_2:
+	ld.global.v2.u32 	{%r106, %r107}, [pixelID];
+	ld.global.v2.u32 	{%r109, %r110}, [tileInfo];
+	add.s32 	%r2, %r106, %r109;
+	add.s32 	%r3, %r107, %r110;
+	setp.eq.f32	%p6, %f765, 0f00000000;
+	setp.eq.f32	%p7, %f764, 0f00000000;
+	and.pred  	%p8, %p7, %p6;
+	setp.eq.f32	%p9, %f766, 0f00000000;
+	and.pred  	%p10, %p8, %p9;
+	@%p10 bra 	BB0_121;
+	bra.uni 	BB0_3;
+
+BB0_121:
+	ld.global.u32 	%r387, [imageEnabled];
+	and.b32  	%r312, %r387, 1;
+	setp.eq.b32	%p116, %r312, 1;
+	@!%p116 bra 	BB0_123;
+	bra.uni 	BB0_122;
+
+BB0_122:
+	cvt.u64.u32	%rd169, %r2;
+	cvt.u64.u32	%rd170, %r3;
+	mov.u64 	%rd173, image;
+	cvta.global.u64 	%rd168, %rd173;
+	// inline asm
+	call (%rd167), _rt_buffer_get_64, (%rd168, %r99, %r100, %rd169, %rd170, %rd25, %rd25);
+	// inline asm
+	mov.u16 	%rs84, 0;
+	st.v4.u8 	[%rd167], {%rs84, %rs84, %rs84, %rs84};
+	ld.global.u32 	%r387, [imageEnabled];
+
+BB0_123:
+	and.b32  	%r315, %r387, 8;
+	setp.eq.s32	%p117, %r315, 0;
+	@%p117 bra 	BB0_125;
+
+	cvt.u64.u32	%rd177, %r3;
+	cvt.u64.u32	%rd176, %r2;
+	mov.u64 	%rd180, image_Mask;
+	cvta.global.u64 	%rd175, %rd180;
+	// inline asm
+	call (%rd174), _rt_buffer_get_64, (%rd175, %r99, %r99, %rd176, %rd177, %rd25, %rd25);
+	// inline asm
+	mov.f32 	%f686, 0f00000000;
+	cvt.rzi.u32.f32	%r318, %f686;
+	cvt.u16.u32	%rs85, %r318;
+	mov.u16 	%rs86, 0;
+	st.v2.u8 	[%rd174], {%rs85, %rs86};
+	ld.global.u32 	%r387, [imageEnabled];
+
+BB0_125:
+	cvt.u64.u32	%rd18, %r2;
+	cvt.u64.u32	%rd19, %r3;
+	and.b32  	%r319, %r387, 4;
+	setp.eq.s32	%p118, %r319, 0;
+	@%p118 bra 	BB0_129;
+
+	ld.global.u32 	%r320, [additive];
+	setp.eq.s32	%p119, %r320, 0;
+	@%p119 bra 	BB0_128;
+
+	mov.u64 	%rd193, image_HDR;
+	cvta.global.u64 	%rd182, %rd193;
+	mov.u32 	%r324, 8;
+	// inline asm
+	call (%rd181), _rt_buffer_get_64, (%rd182, %r99, %r324, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	ld.v4.u16 	{%rs93, %rs94, %rs95, %rs96}, [%rd181];
+	// inline asm
+	{  cvt.f32.f16 %f687, %rs93;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f688, %rs94;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f689, %rs95;}
+
+	// inline asm
+	// inline asm
+	call (%rd187), _rt_buffer_get_64, (%rd182, %r99, %r324, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	add.f32 	%f690, %f687, 0f00000000;
+	add.f32 	%f691, %f688, 0f00000000;
+	add.f32 	%f692, %f689, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs92, %f692;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs91, %f691;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs90, %f690;}
+
+	// inline asm
+	mov.u16 	%rs97, 0;
+	st.v4.u16 	[%rd187], {%rs90, %rs91, %rs92, %rs97};
+	bra.uni 	BB0_129;
+
+BB0_3:
+	ld.global.f32 	%f9, [directDir+8];
+	ld.global.f32 	%f8, [directDir+4];
+	ld.global.f32 	%f7, [directDir];
+	mul.f32 	%f149, %f764, %f7;
+	mul.f32 	%f150, %f765, %f8;
+	neg.f32 	%f151, %f150;
+	sub.f32 	%f152, %f151, %f149;
+	mul.f32 	%f153, %f766, %f9;
+	sub.f32 	%f10, %f152, %f153;
+	ld.global.v2.u32 	{%r118, %r119}, [pixelID];
+	cvt.u64.u32	%rd29, %r118;
+	cvt.u64.u32	%rd30, %r119;
+	mov.u64 	%rd39, uvpos;
+	cvta.global.u64 	%rd28, %rd39;
+	mov.u32 	%r115, 12;
+	// inline asm
+	call (%rd27), _rt_buffer_get_64, (%rd28, %r99, %r115, %rd29, %rd30, %rd25, %rd25);
+	// inline asm
+	ld.f32 	%f154, [%rd27+8];
+	ld.f32 	%f155, [%rd27+4];
+	ld.f32 	%f156, [%rd27];
+	mul.f32 	%f157, %f156, 0f3456BF95;
+	mul.f32 	%f158, %f155, 0f3456BF95;
+	mul.f32 	%f159, %f154, 0f3456BF95;
+	abs.f32 	%f160, %f764;
+	div.rn.f32 	%f161, %f157, %f160;
+	abs.f32 	%f162, %f765;
+	div.rn.f32 	%f163, %f158, %f162;
+	abs.f32 	%f164, %f766;
+	div.rn.f32 	%f165, %f159, %f164;
+	abs.f32 	%f166, %f161;
+	abs.f32 	%f167, %f163;
+	abs.f32 	%f168, %f165;
+	mov.f32 	%f169, 0f38D1B717;
+	max.f32 	%f170, %f166, %f169;
+	max.f32 	%f171, %f167, %f169;
+	max.f32 	%f172, %f168, %f169;
+	fma.rn.f32 	%f11, %f764, %f170, %f156;
+	fma.rn.f32 	%f12, %f765, %f171, %f155;
+	fma.rn.f32 	%f13, %f766, %f172, %f154;
+	abs.f32 	%f173, %f7;
+	abs.f32 	%f174, %f9;
+	setp.gt.f32	%p11, %f173, %f174;
+	neg.f32 	%f175, %f8;
+	neg.f32 	%f176, %f9;
+	selp.f32	%f177, %f175, 0f00000000, %p11;
+	selp.f32	%f178, %f7, %f176, %p11;
+	selp.f32	%f179, 0f00000000, %f8, %p11;
+	mul.f32 	%f180, %f178, %f178;
+	fma.rn.f32 	%f181, %f177, %f177, %f180;
+	fma.rn.f32 	%f182, %f179, %f179, %f181;
+	sqrt.rn.f32 	%f183, %f182;
+	rcp.rn.f32 	%f184, %f183;
+	mul.f32 	%f14, %f177, %f184;
+	mul.f32 	%f15, %f178, %f184;
+	mul.f32 	%f16, %f179, %f184;
+	ld.global.v2.u32 	{%r122, %r123}, [pixelID];
+	cvt.u64.u32	%rd35, %r122;
+	cvt.u64.u32	%rd36, %r123;
+	mov.u64 	%rd40, rnd_seeds;
+	cvta.global.u64 	%rd34, %rd40;
+	// inline asm
+	call (%rd33), _rt_buffer_get_64, (%rd34, %r99, %r100, %rd35, %rd36, %rd25, %rd25);
+	// inline asm
+	ld.global.u32 	%r356, [samples];
+	mov.f32 	%f781, 0f00000000;
+	setp.lt.s32	%p12, %r356, 1;
+	@%p12 bra 	BB0_55;
+
+	cvt.rn.f32.s32	%f186, %r356;
+	rcp.rn.f32 	%f17, %f186;
+	ld.u32 	%r382, [%rd33];
+	mul.f32 	%f18, %f11, 0f3456BF95;
+	mul.f32 	%f19, %f12, 0f3456BF95;
+	mul.f32 	%f20, %f13, 0f3456BF95;
+	mul.f32 	%f187, %f7, %f15;
+	mul.f32 	%f188, %f8, %f14;
+	sub.f32 	%f21, %f188, %f187;
+	mul.f32 	%f189, %f9, %f14;
+	mul.f32 	%f190, %f7, %f16;
+	sub.f32 	%f22, %f190, %f189;
+	mul.f32 	%f191, %f8, %f16;
+	mul.f32 	%f192, %f9, %f15;
+	sub.f32 	%f23, %f192, %f191;
+	mov.f32 	%f781, 0f00000000;
+	mov.u32 	%r357, 0;
+	abs.f32 	%f193, %f19;
+	abs.f32 	%f194, %f18;
+	max.f32 	%f195, %f194, %f193;
+	abs.f32 	%f196, %f20;
+	max.f32 	%f197, %f195, %f196;
+
+BB0_5:
+	setp.lt.s32	%p13, %r356, 1;
+	@%p13 bra 	BB0_54;
+
+	cvt.rn.f32.s32	%f25, %r357;
+	max.f32 	%f26, %f197, %f169;
+	mov.u32 	%r359, 0;
+
+BB0_7:
+	mad.lo.s32 	%r128, %r382, 1664525, 1013904223;
+	and.b32  	%r129, %r128, 16777215;
+	cvt.rn.f32.u32	%f199, %r129;
+	fma.rn.f32 	%f200, %f199, 0f33800000, %f25;
+	mul.f32 	%f201, %f17, %f200;
+	mad.lo.s32 	%r382, %r128, 1664525, 1013904223;
+	and.b32  	%r130, %r382, 16777215;
+	cvt.rn.f32.u32	%f202, %r130;
+	cvt.rn.f32.s32	%f203, %r359;
+	fma.rn.f32 	%f204, %f202, 0f33800000, %f203;
+	mul.f32 	%f205, %f17, %f204;
+	sqrt.rn.f32 	%f28, %f201;
+	mul.f32 	%f775, %f205, 0f40C90FDB;
+	abs.f32 	%f30, %f775;
+	setp.neu.f32	%p14, %f30, 0f7F800000;
+	mov.f32 	%f769, %f775;
+	@%p14 bra 	BB0_9;
+
+	mov.f32 	%f206, 0f00000000;
+	mul.rn.f32 	%f769, %f775, %f206;
+
+BB0_9:
+	mul.f32 	%f207, %f769, 0f3F22F983;
+	cvt.rni.s32.f32	%r370, %f207;
+	cvt.rn.f32.s32	%f208, %r370;
+	neg.f32 	%f209, %f208;
+	mov.f32 	%f210, 0f3FC90FDA;
+	fma.rn.f32 	%f211, %f209, %f210, %f769;
+	mov.f32 	%f212, 0f33A22168;
+	fma.rn.f32 	%f213, %f209, %f212, %f211;
+	mov.f32 	%f214, 0f27C234C5;
+	fma.rn.f32 	%f770, %f209, %f214, %f213;
+	abs.f32 	%f215, %f769;
+	setp.leu.f32	%p15, %f215, 0f47CE4780;
+	@%p15 bra 	BB0_20;
+
+	mov.b32 	 %r13, %f769;
+	shr.u32 	%r14, %r13, 23;
+	shl.b32 	%r133, %r13, 8;
+	or.b32  	%r15, %r133, -2147483648;
+	add.u64 	%rd42, %SP, 4;
+	cvta.to.local.u64 	%rd282, %rd42;
+	mov.u32 	%r362, 0;
+	mov.u64 	%rd281, __cudart_i2opi_f;
+	mov.u32 	%r361, -6;
+
+BB0_11:
+	.pragma "nounroll";
+	ld.const.u32 	%r136, [%rd281];
+	// inline asm
+	{
+	mad.lo.cc.u32   %r134, %r136, %r15, %r362;
+	madc.hi.u32     %r362, %r136, %r15,  0;
+	}
+	// inline asm
+	st.local.u32 	[%rd282], %r134;
+	add.s64 	%rd282, %rd282, 4;
+	add.s64 	%rd281, %rd281, 4;
+	add.s32 	%r361, %r361, 1;
+	setp.ne.s32	%p16, %r361, 0;
+	@%p16 bra 	BB0_11;
+
+	and.b32  	%r139, %r14, 255;
+	add.s32 	%r140, %r139, -128;
+	shr.u32 	%r141, %r140, 5;
+	and.b32  	%r20, %r13, -2147483648;
+	cvta.to.local.u64 	%rd44, %rd42;
+	st.local.u32 	[%rd44+24], %r362;
+	mov.u32 	%r142, 6;
+	sub.s32 	%r143, %r142, %r141;
+	mul.wide.s32 	%rd45, %r143, 4;
+	add.s64 	%rd8, %rd44, %rd45;
+	ld.local.u32 	%r363, [%rd8];
+	ld.local.u32 	%r364, [%rd8+-4];
+	and.b32  	%r23, %r14, 31;
+	setp.eq.s32	%p17, %r23, 0;
+	@%p17 bra 	BB0_14;
+
+	mov.u32 	%r144, 32;
+	sub.s32 	%r145, %r144, %r23;
+	shr.u32 	%r146, %r364, %r145;
+	shl.b32 	%r147, %r363, %r23;
+	add.s32 	%r363, %r146, %r147;
+	ld.local.u32 	%r148, [%rd8+-8];
+	shr.u32 	%r149, %r148, %r145;
+	shl.b32 	%r150, %r364, %r23;
+	add.s32 	%r364, %r149, %r150;
+
+BB0_14:
+	shr.u32 	%r151, %r364, 30;
+	shl.b32 	%r152, %r363, 2;
+	add.s32 	%r365, %r151, %r152;
+	shl.b32 	%r29, %r364, 2;
+	shr.u32 	%r153, %r365, 31;
+	shr.u32 	%r154, %r363, 30;
+	add.s32 	%r30, %r153, %r154;
+	setp.eq.s32	%p18, %r153, 0;
+	@%p18 bra 	BB0_15;
+	bra.uni 	BB0_16;
+
+BB0_15:
+	mov.u32 	%r366, %r20;
+	mov.u32 	%r367, %r29;
+	bra.uni 	BB0_17;
+
+BB0_16:
+	not.b32 	%r155, %r365;
+	neg.s32 	%r367, %r29;
+	setp.eq.s32	%p19, %r29, 0;
+	selp.u32	%r156, 1, 0, %p19;
+	add.s32 	%r365, %r156, %r155;
+	xor.b32  	%r366, %r20, -2147483648;
+
+BB0_17:
+	clz.b32 	%r369, %r365;
+	setp.eq.s32	%p20, %r369, 0;
+	shl.b32 	%r157, %r365, %r369;
+	mov.u32 	%r158, 32;
+	sub.s32 	%r159, %r158, %r369;
+	shr.u32 	%r160, %r367, %r159;
+	add.s32 	%r161, %r160, %r157;
+	selp.b32	%r38, %r365, %r161, %p20;
+	mov.u32 	%r162, -921707870;
+	mul.hi.u32 	%r368, %r38, %r162;
+	setp.eq.s32	%p21, %r20, 0;
+	neg.s32 	%r163, %r30;
+	selp.b32	%r370, %r30, %r163, %p21;
+	setp.lt.s32	%p22, %r368, 1;
+	@%p22 bra 	BB0_19;
+
+	mul.lo.s32 	%r164, %r38, -921707870;
+	shr.u32 	%r165, %r164, 31;
+	shl.b32 	%r166, %r368, 1;
+	add.s32 	%r368, %r165, %r166;
+	add.s32 	%r369, %r369, 1;
+
+BB0_19:
+	mov.u32 	%r167, 126;
+	sub.s32 	%r168, %r167, %r369;
+	shl.b32 	%r169, %r168, 23;
+	add.s32 	%r170, %r368, 1;
+	shr.u32 	%r171, %r170, 7;
+	add.s32 	%r172, %r171, 1;
+	shr.u32 	%r173, %r172, 1;
+	add.s32 	%r174, %r173, %r169;
+	or.b32  	%r175, %r174, %r366;
+	mov.b32 	 %f770, %r175;
+
+BB0_20:
+	mul.rn.f32 	%f36, %f770, %f770;
+	add.s32 	%r46, %r370, 1;
+	and.b32  	%r47, %r46, 1;
+	setp.eq.s32	%p23, %r47, 0;
+	@%p23 bra 	BB0_22;
+	bra.uni 	BB0_21;
+
+BB0_22:
+	mov.f32 	%f218, 0f3C08839E;
+	mov.f32 	%f219, 0fB94CA1F9;
+	fma.rn.f32 	%f771, %f219, %f36, %f218;
+	bra.uni 	BB0_23;
+
+BB0_21:
+	mov.f32 	%f216, 0fBAB6061A;
+	mov.f32 	%f217, 0f37CCF5CE;
+	fma.rn.f32 	%f771, %f217, %f36, %f216;
+
+BB0_23:
+	@%p23 bra 	BB0_25;
+	bra.uni 	BB0_24;
+
+BB0_25:
+	mov.f32 	%f223, 0fBE2AAAA3;
+	fma.rn.f32 	%f224, %f771, %f36, %f223;
+	mov.f32 	%f225, 0f00000000;
+	fma.rn.f32 	%f772, %f224, %f36, %f225;
+	bra.uni 	BB0_26;
+
+BB0_24:
+	mov.f32 	%f220, 0f3D2AAAA5;
+	fma.rn.f32 	%f221, %f771, %f36, %f220;
+	mov.f32 	%f222, 0fBF000000;
+	fma.rn.f32 	%f772, %f221, %f36, %f222;
+
+BB0_26:
+	fma.rn.f32 	%f773, %f772, %f770, %f770;
+	@%p23 bra 	BB0_28;
+
+	mov.f32 	%f226, 0f3F800000;
+	fma.rn.f32 	%f773, %f772, %f36, %f226;
+
+BB0_28:
+	and.b32  	%r176, %r46, 2;
+	setp.eq.s32	%p26, %r176, 0;
+	@%p26 bra 	BB0_30;
+
+	mov.f32 	%f227, 0f00000000;
+	mov.f32 	%f228, 0fBF800000;
+	fma.rn.f32 	%f773, %f773, %f228, %f227;
+
+BB0_30:
+	@%p14 bra 	BB0_32;
+
+	mov.f32 	%f229, 0f00000000;
+	mul.rn.f32 	%f775, %f775, %f229;
+
+BB0_32:
+	mul.f32 	%f230, %f775, 0f3F22F983;
+	cvt.rni.s32.f32	%r380, %f230;
+	cvt.rn.f32.s32	%f231, %r380;
+	neg.f32 	%f232, %f231;
+	fma.rn.f32 	%f234, %f232, %f210, %f775;
+	fma.rn.f32 	%f236, %f232, %f212, %f234;
+	fma.rn.f32 	%f776, %f232, %f214, %f236;
+	abs.f32 	%f238, %f775;
+	setp.leu.f32	%p28, %f238, 0f47CE4780;
+	@%p28 bra 	BB0_43;
+
+	mov.b32 	 %r49, %f775;
+	shr.u32 	%r50, %r49, 23;
+	shl.b32 	%r179, %r49, 8;
+	or.b32  	%r51, %r179, -2147483648;
+	add.u64 	%rd47, %SP, 4;
+	cvta.to.local.u64 	%rd284, %rd47;
+	mov.u32 	%r372, 0;
+	mov.u64 	%rd283, __cudart_i2opi_f;
+	mov.u32 	%r371, -6;
+
+BB0_34:
+	.pragma "nounroll";
+	ld.const.u32 	%r182, [%rd283];
+	// inline asm
+	{
+	mad.lo.cc.u32   %r180, %r182, %r51, %r372;
+	madc.hi.u32     %r372, %r182, %r51,  0;
+	}
+	// inline asm
+	st.local.u32 	[%rd284], %r180;
+	add.s64 	%rd284, %rd284, 4;
+	add.s64 	%rd283, %rd283, 4;
+	add.s32 	%r371, %r371, 1;
+	setp.ne.s32	%p29, %r371, 0;
+	@%p29 bra 	BB0_34;
+
+	and.b32  	%r185, %r50, 255;
+	add.s32 	%r186, %r185, -128;
+	shr.u32 	%r187, %r186, 5;
+	and.b32  	%r56, %r49, -2147483648;
+	cvta.to.local.u64 	%rd49, %rd47;
+	st.local.u32 	[%rd49+24], %r372;
+	mov.u32 	%r188, 6;
+	sub.s32 	%r189, %r188, %r187;
+	mul.wide.s32 	%rd50, %r189, 4;
+	add.s64 	%rd14, %rd49, %rd50;
+	ld.local.u32 	%r373, [%rd14];
+	ld.local.u32 	%r374, [%rd14+-4];
+	and.b32  	%r59, %r50, 31;
+	setp.eq.s32	%p30, %r59, 0;
+	@%p30 bra 	BB0_37;
+
+	mov.u32 	%r190, 32;
+	sub.s32 	%r191, %r190, %r59;
+	shr.u32 	%r192, %r374, %r191;
+	shl.b32 	%r193, %r373, %r59;
+	add.s32 	%r373, %r192, %r193;
+	ld.local.u32 	%r194, [%rd14+-8];
+	shr.u32 	%r195, %r194, %r191;
+	shl.b32 	%r196, %r374, %r59;
+	add.s32 	%r374, %r195, %r196;
+
+BB0_37:
+	shr.u32 	%r197, %r374, 30;
+	shl.b32 	%r198, %r373, 2;
+	add.s32 	%r375, %r197, %r198;
+	shl.b32 	%r65, %r374, 2;
+	shr.u32 	%r199, %r375, 31;
+	shr.u32 	%r200, %r373, 30;
+	add.s32 	%r66, %r199, %r200;
+	setp.eq.s32	%p31, %r199, 0;
+	@%p31 bra 	BB0_38;
+	bra.uni 	BB0_39;
+
+BB0_38:
+	mov.u32 	%r376, %r56;
+	mov.u32 	%r377, %r65;
+	bra.uni 	BB0_40;
+
+BB0_39:
+	not.b32 	%r201, %r375;
+	neg.s32 	%r377, %r65;
+	setp.eq.s32	%p32, %r65, 0;
+	selp.u32	%r202, 1, 0, %p32;
+	add.s32 	%r375, %r202, %r201;
+	xor.b32  	%r376, %r56, -2147483648;
+
+BB0_40:
+	clz.b32 	%r379, %r375;
+	setp.eq.s32	%p33, %r379, 0;
+	shl.b32 	%r203, %r375, %r379;
+	mov.u32 	%r204, 32;
+	sub.s32 	%r205, %r204, %r379;
+	shr.u32 	%r206, %r377, %r205;
+	add.s32 	%r207, %r206, %r203;
+	selp.b32	%r74, %r375, %r207, %p33;
+	mov.u32 	%r208, -921707870;
+	mul.hi.u32 	%r378, %r74, %r208;
+	setp.eq.s32	%p34, %r56, 0;
+	neg.s32 	%r209, %r66;
+	selp.b32	%r380, %r66, %r209, %p34;
+	setp.lt.s32	%p35, %r378, 1;
+	@%p35 bra 	BB0_42;
+
+	mul.lo.s32 	%r210, %r74, -921707870;
+	shr.u32 	%r211, %r210, 31;
+	shl.b32 	%r212, %r378, 1;
+	add.s32 	%r378, %r211, %r212;
+	add.s32 	%r379, %r379, 1;
+
+BB0_42:
+	mov.u32 	%r213, 126;
+	sub.s32 	%r214, %r213, %r379;
+	shl.b32 	%r215, %r214, 23;
+	add.s32 	%r216, %r378, 1;
+	shr.u32 	%r217, %r216, 7;
+	add.s32 	%r218, %r217, 1;
+	shr.u32 	%r219, %r218, 1;
+	add.s32 	%r220, %r219, %r215;
+	or.b32  	%r221, %r220, %r376;
+	mov.b32 	 %f776, %r221;
+
+BB0_43:
+	mul.rn.f32 	%f53, %f776, %f776;
+	and.b32  	%r82, %r380, 1;
+	setp.eq.s32	%p36, %r82, 0;
+	@%p36 bra 	BB0_45;
+	bra.uni 	BB0_44;
+
+BB0_45:
+	mov.f32 	%f241, 0f3C08839E;
+	mov.f32 	%f242, 0fB94CA1F9;
+	fma.rn.f32 	%f777, %f242, %f53, %f241;
+	bra.uni 	BB0_46;
+
+BB0_44:
+	mov.f32 	%f239, 0fBAB6061A;
+	mov.f32 	%f240, 0f37CCF5CE;
+	fma.rn.f32 	%f777, %f240, %f53, %f239;
+
+BB0_46:
+	@%p36 bra 	BB0_48;
+	bra.uni 	BB0_47;
+
+BB0_48:
+	mov.f32 	%f246, 0fBE2AAAA3;
+	fma.rn.f32 	%f247, %f777, %f53, %f246;
+	mov.f32 	%f248, 0f00000000;
+	fma.rn.f32 	%f778, %f247, %f53, %f248;
+	bra.uni 	BB0_49;
+
+BB0_47:
+	mov.f32 	%f243, 0f3D2AAAA5;
+	fma.rn.f32 	%f244, %f777, %f53, %f243;
+	mov.f32 	%f245, 0fBF000000;
+	fma.rn.f32 	%f778, %f244, %f53, %f245;
+
+BB0_49:
+	fma.rn.f32 	%f779, %f778, %f776, %f776;
+	@%p36 bra 	BB0_51;
+
+	mov.f32 	%f249, 0f3F800000;
+	fma.rn.f32 	%f779, %f778, %f53, %f249;
+
+BB0_51:
+	and.b32  	%r222, %r380, 2;
+	setp.eq.s32	%p39, %r222, 0;
+	@%p39 bra 	BB0_53;
+
+	mov.f32 	%f250, 0f00000000;
+	mov.f32 	%f251, 0fBF800000;
+	fma.rn.f32 	%f779, %f779, %f251, %f250;
+
+BB0_53:
+	mul.f32 	%f260, %f28, %f773;
+	add.u64 	%rd51, %SP, 0;
+	cvta.to.local.u64 	%rd52, %rd51;
+	mul.f32 	%f261, %f260, %f260;
+	mov.f32 	%f262, 0f3F800000;
+	sub.f32 	%f263, %f262, %f261;
+	mul.f32 	%f264, %f28, %f779;
+	mul.f32 	%f265, %f264, %f264;
+	sub.f32 	%f266, %f263, %f265;
+	mov.f32 	%f267, 0f00000000;
+	max.f32 	%f268, %f267, %f266;
+	sqrt.rn.f32 	%f269, %f268;
+	mul.f32 	%f270, %f14, %f264;
+	mul.f32 	%f271, %f15, %f264;
+	mul.f32 	%f272, %f16, %f264;
+	fma.rn.f32 	%f273, %f23, %f260, %f270;
+	fma.rn.f32 	%f274, %f22, %f260, %f271;
+	fma.rn.f32 	%f275, %f21, %f260, %f272;
+	fma.rn.f32 	%f276, %f7, %f269, %f273;
+	fma.rn.f32 	%f277, %f8, %f269, %f274;
+	fma.rn.f32 	%f278, %f9, %f269, %f275;
+	add.f32 	%f279, %f7, %f276;
+	add.f32 	%f280, %f8, %f277;
+	add.f32 	%f281, %f9, %f278;
+	ld.global.f32 	%f282, [shadowSpread];
+	mul.f32 	%f283, %f282, %f279;
+	mul.f32 	%f284, %f282, %f280;
+	mul.f32 	%f285, %f282, %f281;
+	sub.f32 	%f286, %f283, %f7;
+	sub.f32 	%f287, %f284, %f8;
+	sub.f32 	%f288, %f285, %f9;
+	mul.f32 	%f289, %f287, %f287;
+	fma.rn.f32 	%f290, %f286, %f286, %f289;
+	fma.rn.f32 	%f291, %f288, %f288, %f290;
+	sqrt.rn.f32 	%f292, %f291;
+	rcp.rn.f32 	%f293, %f292;
+	mul.f32 	%f255, %f293, %f286;
+	mul.f32 	%f256, %f293, %f287;
+	mul.f32 	%f257, %f293, %f288;
+	ld.global.u32 	%r226, [imageEnabled];
+	and.b32  	%r227, %r226, 32;
+	setp.eq.s32	%p40, %r227, 0;
+	selp.f32	%f294, 0f3F800000, 0f41200000, %p40;
+	mul.f32 	%f258, %f294, %f26;
+	mov.u32 	%r228, 1065353216;
+	st.local.u32 	[%rd52], %r228;
+	ld.global.u32 	%r223, [root];
+	mov.u32 	%r224, 1;
+	mov.f32 	%f259, 0f6C4ECB8F;
+	// inline asm
+	call _rt_trace_64, (%r223, %f11, %f12, %f13, %f255, %f256, %f257, %r224, %f258, %f259, %rd51, %r100);
+	// inline asm
+	ld.local.f32 	%f295, [%rd52];
+	add.f32 	%f781, %f781, %f295;
+	ld.global.u32 	%r356, [samples];
+	add.s32 	%r359, %r359, 1;
+	setp.lt.s32	%p41, %r359, %r356;
+	@%p41 bra 	BB0_7;
+
+BB0_54:
+	add.s32 	%r357, %r357, 1;
+	setp.lt.s32	%p42, %r357, %r356;
+	@%p42 bra 	BB0_5;
+
+BB0_55:
+	setp.eq.s32	%p43, %r356, 0;
+	mov.f32 	%f783, 0f3F800000;
+	@%p43 bra 	BB0_57;
+
+	mul.lo.s32 	%r229, %r356, %r356;
+	cvt.rn.f32.s32	%f297, %r229;
+	div.rn.f32 	%f783, %f781, %f297;
+
+BB0_57:
+	ld.global.f32 	%f298, [directColor];
+	mul.f32 	%f299, %f783, %f298;
+	ld.global.f32 	%f300, [directColor+4];
+	mul.f32 	%f301, %f783, %f300;
+	ld.global.f32 	%f302, [directColor+8];
+	mul.f32 	%f303, %f783, %f302;
+	cvt.sat.f32.f32	%f304, %f10;
+	mul.f32 	%f70, %f299, %f304;
+	mul.f32 	%f71, %f301, %f304;
+	mul.f32 	%f72, %f303, %f304;
+	mul.f32 	%f305, %f10, 0f40800000;
+	cvt.sat.f32.f32	%f306, %f305;
+	mul.f32 	%f307, %f299, %f306;
+	mul.f32 	%f308, %f301, %f306;
+	mul.f32 	%f309, %f303, %f306;
+	mul.f32 	%f73, %f307, 0f3E800000;
+	mul.f32 	%f74, %f308, 0f3E800000;
+	mul.f32 	%f75, %f309, 0f3E800000;
+	ld.global.u32 	%r385, [imageEnabled];
+	and.b32  	%r230, %r385, 8;
+	setp.eq.s32	%p44, %r230, 0;
+	@%p44 bra 	BB0_70;
+
+	cvt.u64.u32	%rd55, %r2;
+	cvt.u64.u32	%rd56, %r3;
+	mov.u64 	%rd59, image_Mask;
+	cvta.global.u64 	%rd54, %rd59;
+	// inline asm
+	call (%rd53), _rt_buffer_get_64, (%rd54, %r99, %r99, %rd55, %rd56, %rd25, %rd25);
+	// inline asm
+	abs.f32 	%f77, %f783;
+	setp.lt.f32	%p45, %f77, 0f00800000;
+	mul.f32 	%f315, %f77, 0f4B800000;
+	selp.f32	%f316, 0fC3170000, 0fC2FE0000, %p45;
+	selp.f32	%f317, %f315, %f77, %p45;
+	mov.b32 	 %r233, %f317;
+	and.b32  	%r234, %r233, 8388607;
+	or.b32  	%r235, %r234, 1065353216;
+	mov.b32 	 %f318, %r235;
+	shr.u32 	%r236, %r233, 23;
+	cvt.rn.f32.u32	%f319, %r236;
+	add.f32 	%f320, %f316, %f319;
+	setp.gt.f32	%p46, %f318, 0f3FB504F3;
+	mul.f32 	%f321, %f318, 0f3F000000;
+	add.f32 	%f322, %f320, 0f3F800000;
+	selp.f32	%f323, %f321, %f318, %p46;
+	selp.f32	%f324, %f322, %f320, %p46;
+	add.f32 	%f325, %f323, 0fBF800000;
+	add.f32 	%f311, %f323, 0f3F800000;
+	// inline asm
+	rcp.approx.ftz.f32 %f310,%f311;
+	// inline asm
+	add.f32 	%f326, %f325, %f325;
+	mul.f32 	%f327, %f310, %f326;
+	mul.f32 	%f328, %f327, %f327;
+	mov.f32 	%f329, 0f3C4CAF63;
+	mov.f32 	%f330, 0f3B18F0FE;
+	fma.rn.f32 	%f331, %f330, %f328, %f329;
+	mov.f32 	%f332, 0f3DAAAABD;
+	fma.rn.f32 	%f333, %f331, %f328, %f332;
+	mul.rn.f32 	%f334, %f333, %f328;
+	mul.rn.f32 	%f335, %f334, %f327;
+	sub.f32 	%f336, %f325, %f327;
+	neg.f32 	%f337, %f327;
+	add.f32 	%f338, %f336, %f336;
+	fma.rn.f32 	%f339, %f337, %f325, %f338;
+	mul.rn.f32 	%f340, %f310, %f339;
+	add.f32 	%f341, %f335, %f327;
+	sub.f32 	%f342, %f327, %f341;
+	add.f32 	%f343, %f335, %f342;
+	add.f32 	%f344, %f340, %f343;
+	add.f32 	%f345, %f341, %f344;
+	sub.f32 	%f346, %f341, %f345;
+	add.f32 	%f347, %f344, %f346;
+	mov.f32 	%f348, 0f3F317200;
+	mul.rn.f32 	%f349, %f324, %f348;
+	mov.f32 	%f350, 0f35BFBE8E;
+	mul.rn.f32 	%f351, %f324, %f350;
+	add.f32 	%f352, %f349, %f345;
+	sub.f32 	%f353, %f349, %f352;
+	add.f32 	%f354, %f345, %f353;
+	add.f32 	%f355, %f347, %f354;
+	add.f32 	%f356, %f351, %f355;
+	add.f32 	%f357, %f352, %f356;
+	sub.f32 	%f358, %f352, %f357;
+	add.f32 	%f359, %f356, %f358;
+	mov.f32 	%f360, 0f3EE8BA2E;
+	mul.rn.f32 	%f361, %f360, %f357;
+	neg.f32 	%f362, %f361;
+	fma.rn.f32 	%f363, %f360, %f357, %f362;
+	fma.rn.f32 	%f364, %f360, %f359, %f363;
+	mov.f32 	%f365, 0f00000000;
+	fma.rn.f32 	%f366, %f365, %f357, %f364;
+	add.rn.f32 	%f367, %f361, %f366;
+	neg.f32 	%f368, %f367;
+	add.rn.f32 	%f369, %f361, %f368;
+	add.rn.f32 	%f370, %f369, %f366;
+	mov.b32 	 %r237, %f367;
+	setp.eq.s32	%p47, %r237, 1118925336;
+	add.s32 	%r238, %r237, -1;
+	mov.b32 	 %f371, %r238;
+	add.f32 	%f372, %f370, 0f37000000;
+	selp.f32	%f373, %f371, %f367, %p47;
+	selp.f32	%f78, %f372, %f370, %p47;
+	mul.f32 	%f374, %f373, 0f3FB8AA3B;
+	cvt.rzi.f32.f32	%f375, %f374;
+	mov.f32 	%f376, 0fBF317200;
+	fma.rn.f32 	%f377, %f375, %f376, %f373;
+	mov.f32 	%f378, 0fB5BFBE8E;
+	fma.rn.f32 	%f379, %f375, %f378, %f377;
+	mul.f32 	%f380, %f379, 0f3FB8AA3B;
+	ex2.approx.ftz.f32 	%f381, %f380;
+	add.f32 	%f382, %f375, 0f00000000;
+	ex2.approx.f32 	%f383, %f382;
+	mul.f32 	%f384, %f381, %f383;
+	setp.lt.f32	%p48, %f373, 0fC2D20000;
+	selp.f32	%f385, 0f00000000, %f384, %p48;
+	setp.gt.f32	%p49, %f373, 0f42D20000;
+	selp.f32	%f784, 0f7F800000, %f385, %p49;
+	setp.eq.f32	%p50, %f784, 0f7F800000;
+	@%p50 bra 	BB0_60;
+
+	fma.rn.f32 	%f784, %f784, %f78, %f784;
+
+BB0_60:
+	mov.f32 	%f756, 0f3E68BA2E;
+	cvt.rzi.f32.f32	%f755, %f756;
+	fma.rn.f32 	%f754, %f755, 0fC0000000, 0f3EE8BA2E;
+	abs.f32 	%f753, %f754;
+	setp.lt.f32	%p51, %f783, 0f00000000;
+	setp.eq.f32	%p52, %f753, 0f3F800000;
+	and.pred  	%p1, %p51, %p52;
+	mov.b32 	 %r239, %f784;
+	xor.b32  	%r240, %r239, -2147483648;
+	mov.b32 	 %f386, %r240;
+	selp.f32	%f786, %f386, %f784, %p1;
+	setp.eq.f32	%p53, %f783, 0f00000000;
+	@%p53 bra 	BB0_63;
+	bra.uni 	BB0_61;
+
+BB0_63:
+	add.f32 	%f389, %f783, %f783;
+	selp.f32	%f786, %f389, 0f00000000, %p52;
+	bra.uni 	BB0_64;
+
+BB0_128:
+	mov.u64 	%rd200, image_HDR;
+	cvta.global.u64 	%rd195, %rd200;
+	mov.u32 	%r326, 8;
+	// inline asm
+	call (%rd194), _rt_buffer_get_64, (%rd195, %r99, %r326, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	mov.f32 	%f693, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs98, %f693;}
+
+	// inline asm
+	mov.u16 	%rs99, 0;
+	st.v4.u16 	[%rd194], {%rs98, %rs98, %rs98, %rs99};
+
+BB0_129:
+	ld.global.u32 	%r327, [additive];
+	setp.eq.s32	%p120, %r327, 0;
+	@%p120 bra 	BB0_131;
+
+	mov.u64 	%rd213, image_RNM0;
+	cvta.global.u64 	%rd202, %rd213;
+	mov.u32 	%r331, 8;
+	// inline asm
+	call (%rd201), _rt_buffer_get_64, (%rd202, %r99, %r331, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	ld.v4.u16 	{%rs106, %rs107, %rs108, %rs109}, [%rd201];
+	// inline asm
+	{  cvt.f32.f16 %f694, %rs106;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f695, %rs107;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f696, %rs108;}
+
+	// inline asm
+	// inline asm
+	call (%rd207), _rt_buffer_get_64, (%rd202, %r99, %r331, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	add.f32 	%f697, %f694, 0f00000000;
+	add.f32 	%f698, %f695, 0f00000000;
+	add.f32 	%f699, %f696, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs105, %f699;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs104, %f698;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs103, %f697;}
+
+	// inline asm
+	mov.u16 	%rs110, 0;
+	st.v4.u16 	[%rd207], {%rs103, %rs104, %rs105, %rs110};
+	bra.uni 	BB0_132;
+
+BB0_131:
+	mov.u64 	%rd220, image_RNM0;
+	cvta.global.u64 	%rd215, %rd220;
+	mov.u32 	%r333, 8;
+	// inline asm
+	call (%rd214), _rt_buffer_get_64, (%rd215, %r99, %r333, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	mov.f32 	%f700, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs111, %f700;}
+
+	// inline asm
+	mov.u16 	%rs112, 0;
+	st.v4.u16 	[%rd214], {%rs111, %rs111, %rs111, %rs112};
+
+BB0_132:
+	ld.global.u32 	%r334, [additive];
+	setp.eq.s32	%p121, %r334, 0;
+	@%p121 bra 	BB0_134;
+
+	mov.u64 	%rd233, image_RNM1;
+	cvta.global.u64 	%rd222, %rd233;
+	mov.u32 	%r338, 8;
+	// inline asm
+	call (%rd221), _rt_buffer_get_64, (%rd222, %r99, %r338, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	ld.v4.u16 	{%rs119, %rs120, %rs121, %rs122}, [%rd221];
+	// inline asm
+	{  cvt.f32.f16 %f701, %rs119;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f702, %rs120;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f703, %rs121;}
+
+	// inline asm
+	// inline asm
+	call (%rd227), _rt_buffer_get_64, (%rd222, %r99, %r338, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	add.f32 	%f704, %f701, 0f00000000;
+	add.f32 	%f705, %f702, 0f00000000;
+	add.f32 	%f706, %f703, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs118, %f706;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs117, %f705;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs116, %f704;}
+
+	// inline asm
+	mov.u16 	%rs123, 0;
+	st.v4.u16 	[%rd227], {%rs116, %rs117, %rs118, %rs123};
+	bra.uni 	BB0_135;
+
+BB0_134:
+	mov.u64 	%rd240, image_RNM1;
+	cvta.global.u64 	%rd235, %rd240;
+	mov.u32 	%r340, 8;
+	// inline asm
+	call (%rd234), _rt_buffer_get_64, (%rd235, %r99, %r340, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	mov.f32 	%f707, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs124, %f707;}
+
+	// inline asm
+	mov.u16 	%rs125, 0;
+	st.v4.u16 	[%rd234], {%rs124, %rs124, %rs124, %rs125};
+
+BB0_135:
+	ld.global.u32 	%r341, [additive];
+	setp.eq.s32	%p122, %r341, 0;
+	@%p122 bra 	BB0_137;
+
+	mov.u64 	%rd253, image_RNM2;
+	cvta.global.u64 	%rd242, %rd253;
+	mov.u32 	%r345, 8;
+	// inline asm
+	call (%rd241), _rt_buffer_get_64, (%rd242, %r99, %r345, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	ld.v4.u16 	{%rs132, %rs133, %rs134, %rs135}, [%rd241];
+	// inline asm
+	{  cvt.f32.f16 %f708, %rs132;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f709, %rs133;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f710, %rs134;}
+
+	// inline asm
+	// inline asm
+	call (%rd247), _rt_buffer_get_64, (%rd242, %r99, %r345, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	add.f32 	%f711, %f708, 0f00000000;
+	add.f32 	%f712, %f709, 0f00000000;
+	add.f32 	%f713, %f710, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs131, %f713;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs130, %f712;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs129, %f711;}
+
+	// inline asm
+	mov.u16 	%rs136, 0;
+	st.v4.u16 	[%rd247], {%rs129, %rs130, %rs131, %rs136};
+	bra.uni 	BB0_138;
+
+BB0_137:
+	mov.u64 	%rd260, image_RNM2;
+	cvta.global.u64 	%rd255, %rd260;
+	mov.u32 	%r347, 8;
+	// inline asm
+	call (%rd254), _rt_buffer_get_64, (%rd255, %r99, %r347, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	mov.f32 	%f714, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs137, %f714;}
+
+	// inline asm
+	mov.u16 	%rs138, 0;
+	st.v4.u16 	[%rd254], {%rs137, %rs137, %rs137, %rs138};
+
+BB0_138:
+	ld.global.u32 	%r348, [additive];
+	setp.eq.s32	%p123, %r348, 0;
+	@%p123 bra 	BB0_140;
+
+	mov.u64 	%rd273, image_RNM3;
+	cvta.global.u64 	%rd262, %rd273;
+	mov.u32 	%r352, 8;
+	// inline asm
+	call (%rd261), _rt_buffer_get_64, (%rd262, %r99, %r352, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	ld.v4.u16 	{%rs145, %rs146, %rs147, %rs148}, [%rd261];
+	// inline asm
+	{  cvt.f32.f16 %f715, %rs145;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f716, %rs146;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f717, %rs147;}
+
+	// inline asm
+	// inline asm
+	call (%rd267), _rt_buffer_get_64, (%rd262, %r99, %r352, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	add.f32 	%f718, %f715, 0f00000000;
+	add.f32 	%f719, %f716, 0f00000000;
+	add.f32 	%f720, %f717, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs144, %f720;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs143, %f719;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs142, %f718;}
+
+	// inline asm
+	mov.u16 	%rs149, 0;
+	st.v4.u16 	[%rd267], {%rs142, %rs143, %rs144, %rs149};
+	bra.uni 	BB0_141;
+
+BB0_140:
+	mov.u64 	%rd280, image_RNM3;
+	cvta.global.u64 	%rd275, %rd280;
+	mov.u32 	%r354, 8;
+	// inline asm
+	call (%rd274), _rt_buffer_get_64, (%rd275, %r99, %r354, %rd18, %rd19, %rd25, %rd25);
+	// inline asm
+	mov.f32 	%f721, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs150, %f721;}
+
+	// inline asm
+	mov.u16 	%rs151, 0;
+	st.v4.u16 	[%rd274], {%rs150, %rs150, %rs150, %rs151};
+	bra.uni 	BB0_141;
+
+BB0_61:
+	setp.geu.f32	%p54, %f783, 0f00000000;
+	@%p54 bra 	BB0_64;
+
+	mov.f32 	%f760, 0f3EE8BA2E;
+	cvt.rzi.f32.f32	%f388, %f760;
+	setp.neu.f32	%p55, %f388, 0f3EE8BA2E;
+	selp.f32	%f786, 0f7FFFFFFF, %f786, %p55;
+
+BB0_64:
+	abs.f32 	%f757, %f783;
+	add.f32 	%f390, %f757, 0f3EE8BA2E;
+	mov.b32 	 %r241, %f390;
+	setp.lt.s32	%p57, %r241, 2139095040;
+	@%p57 bra 	BB0_69;
+
+	abs.f32 	%f758, %f783;
+	setp.gtu.f32	%p58, %f758, 0f7F800000;
+	@%p58 bra 	BB0_68;
+	bra.uni 	BB0_66;
+
+BB0_68:
+	add.f32 	%f786, %f783, 0f3EE8BA2E;
+	bra.uni 	BB0_69;
+
+BB0_66:
+	abs.f32 	%f759, %f783;
+	setp.neu.f32	%p59, %f759, 0f7F800000;
+	@%p59 bra 	BB0_69;
+
+	selp.f32	%f786, 0fFF800000, 0f7F800000, %p1;
+
+BB0_69:
+	mul.f32 	%f391, %f786, 0f437F0000;
+	setp.eq.f32	%p60, %f783, 0f3F800000;
+	selp.f32	%f392, 0f437F0000, %f391, %p60;
+	cvt.rzi.u32.f32	%r242, %f392;
+	cvt.u16.u32	%rs14, %r242;
+	mov.u16 	%rs15, 255;
+	st.v2.u8 	[%rd53], {%rs14, %rs15};
+	ld.global.u32 	%r385, [imageEnabled];
+
+BB0_70:
+	and.b32  	%r243, %r385, 1;
+	setp.eq.b32	%p61, %r243, 1;
+	@!%p61 bra 	BB0_105;
+	bra.uni 	BB0_71;
+
+BB0_71:
+	abs.f32 	%f90, %f70;
+	setp.lt.f32	%p62, %f90, 0f00800000;
+	mul.f32 	%f398, %f90, 0f4B800000;
+	selp.f32	%f399, 0fC3170000, 0fC2FE0000, %p62;
+	selp.f32	%f400, %f398, %f90, %p62;
+	mov.b32 	 %r244, %f400;
+	and.b32  	%r245, %r244, 8388607;
+	or.b32  	%r246, %r245, 1065353216;
+	mov.b32 	 %f401, %r246;
+	shr.u32 	%r247, %r244, 23;
+	cvt.rn.f32.u32	%f402, %r247;
+	add.f32 	%f403, %f399, %f402;
+	setp.gt.f32	%p63, %f401, 0f3FB504F3;
+	mul.f32 	%f404, %f401, 0f3F000000;
+	add.f32 	%f405, %f403, 0f3F800000;
+	selp.f32	%f406, %f404, %f401, %p63;
+	selp.f32	%f407, %f405, %f403, %p63;
+	add.f32 	%f408, %f406, 0fBF800000;
+	add.f32 	%f394, %f406, 0f3F800000;
+	// inline asm
+	rcp.approx.ftz.f32 %f393,%f394;
+	// inline asm
+	add.f32 	%f409, %f408, %f408;
+	mul.f32 	%f410, %f393, %f409;
+	mul.f32 	%f411, %f410, %f410;
+	mov.f32 	%f412, 0f3C4CAF63;
+	mov.f32 	%f413, 0f3B18F0FE;
+	fma.rn.f32 	%f414, %f413, %f411, %f412;
+	mov.f32 	%f415, 0f3DAAAABD;
+	fma.rn.f32 	%f416, %f414, %f411, %f415;
+	mul.rn.f32 	%f417, %f416, %f411;
+	mul.rn.f32 	%f418, %f417, %f410;
+	sub.f32 	%f419, %f408, %f410;
+	neg.f32 	%f420, %f410;
+	add.f32 	%f421, %f419, %f419;
+	fma.rn.f32 	%f422, %f420, %f408, %f421;
+	mul.rn.f32 	%f423, %f393, %f422;
+	add.f32 	%f424, %f418, %f410;
+	sub.f32 	%f425, %f410, %f424;
+	add.f32 	%f426, %f418, %f425;
+	add.f32 	%f427, %f423, %f426;
+	add.f32 	%f428, %f424, %f427;
+	sub.f32 	%f429, %f424, %f428;
+	add.f32 	%f430, %f427, %f429;
+	mov.f32 	%f431, 0f3F317200;
+	mul.rn.f32 	%f432, %f407, %f431;
+	mov.f32 	%f433, 0f35BFBE8E;
+	mul.rn.f32 	%f434, %f407, %f433;
+	add.f32 	%f435, %f432, %f428;
+	sub.f32 	%f436, %f432, %f435;
+	add.f32 	%f437, %f428, %f436;
+	add.f32 	%f438, %f430, %f437;
+	add.f32 	%f439, %f434, %f438;
+	add.f32 	%f440, %f435, %f439;
+	sub.f32 	%f441, %f435, %f440;
+	add.f32 	%f442, %f439, %f441;
+	mov.f32 	%f443, 0f3EE66666;
+	mul.rn.f32 	%f444, %f443, %f440;
+	neg.f32 	%f445, %f444;
+	fma.rn.f32 	%f446, %f443, %f440, %f445;
+	fma.rn.f32 	%f447, %f443, %f442, %f446;
+	mov.f32 	%f448, 0f00000000;
+	fma.rn.f32 	%f449, %f448, %f440, %f447;
+	add.rn.f32 	%f450, %f444, %f449;
+	neg.f32 	%f451, %f450;
+	add.rn.f32 	%f452, %f444, %f451;
+	add.rn.f32 	%f453, %f452, %f449;
+	mov.b32 	 %r248, %f450;
+	setp.eq.s32	%p64, %r248, 1118925336;
+	add.s32 	%r249, %r248, -1;
+	mov.b32 	 %f454, %r249;
+	add.f32 	%f455, %f453, 0f37000000;
+	selp.f32	%f456, %f454, %f450, %p64;
+	selp.f32	%f91, %f455, %f453, %p64;
+	mul.f32 	%f457, %f456, 0f3FB8AA3B;
+	cvt.rzi.f32.f32	%f458, %f457;
+	mov.f32 	%f459, 0fBF317200;
+	fma.rn.f32 	%f460, %f458, %f459, %f456;
+	mov.f32 	%f461, 0fB5BFBE8E;
+	fma.rn.f32 	%f462, %f458, %f461, %f460;
+	mul.f32 	%f463, %f462, 0f3FB8AA3B;
+	ex2.approx.ftz.f32 	%f464, %f463;
+	add.f32 	%f465, %f458, 0f00000000;
+	ex2.approx.f32 	%f466, %f465;
+	mul.f32 	%f467, %f464, %f466;
+	setp.lt.f32	%p65, %f456, 0fC2D20000;
+	selp.f32	%f468, 0f00000000, %f467, %p65;
+	setp.gt.f32	%p66, %f456, 0f42D20000;
+	selp.f32	%f787, 0f7F800000, %f468, %p66;
+	setp.eq.f32	%p67, %f787, 0f7F800000;
+	@%p67 bra 	BB0_73;
+
+	fma.rn.f32 	%f787, %f787, %f91, %f787;
+
+BB0_73:
+	mov.f32 	%f725, 0f3E666666;
+	cvt.rzi.f32.f32	%f724, %f725;
+	fma.rn.f32 	%f723, %f724, 0fC0000000, 0f3EE66666;
+	abs.f32 	%f722, %f723;
+	setp.lt.f32	%p68, %f70, 0f00000000;
+	setp.eq.f32	%p69, %f722, 0f3F800000;
+	and.pred  	%p2, %p68, %p69;
+	mov.b32 	 %r250, %f787;
+	xor.b32  	%r251, %r250, -2147483648;
+	mov.b32 	 %f469, %r251;
+	selp.f32	%f789, %f469, %f787, %p2;
+	setp.eq.f32	%p70, %f70, 0f00000000;
+	@%p70 bra 	BB0_76;
+	bra.uni 	BB0_74;
+
+BB0_76:
+	add.f32 	%f472, %f70, %f70;
+	selp.f32	%f789, %f472, 0f00000000, %p69;
+	bra.uni 	BB0_77;
+
+BB0_74:
+	setp.geu.f32	%p71, %f70, 0f00000000;
+	@%p71 bra 	BB0_77;
+
+	mov.f32 	%f749, 0f3EE66666;
+	cvt.rzi.f32.f32	%f471, %f749;
+	setp.neu.f32	%p72, %f471, 0f3EE66666;
+	selp.f32	%f789, 0f7FFFFFFF, %f789, %p72;
+
+BB0_77:
+	abs.f32 	%f726, %f70;
+	add.f32 	%f473, %f726, 0f3EE66666;
+	mov.b32 	 %r252, %f473;
+	setp.lt.s32	%p74, %r252, 2139095040;
+	@%p74 bra 	BB0_82;
+
+	abs.f32 	%f747, %f70;
+	setp.gtu.f32	%p75, %f747, 0f7F800000;
+	@%p75 bra 	BB0_81;
+	bra.uni 	BB0_79;
+
+BB0_81:
+	add.f32 	%f789, %f70, 0f3EE66666;
+	bra.uni 	BB0_82;
+
+BB0_79:
+	abs.f32 	%f748, %f70;
+	setp.neu.f32	%p76, %f748, 0f7F800000;
+	@%p76 bra 	BB0_82;
+
+	selp.f32	%f789, 0fFF800000, 0f7F800000, %p2;
+
+BB0_82:
+	mov.f32 	%f735, 0fB5BFBE8E;
+	mov.f32 	%f734, 0fBF317200;
+	mov.f32 	%f733, 0f00000000;
+	mov.f32 	%f732, 0f35BFBE8E;
+	mov.f32 	%f731, 0f3F317200;
+	mov.f32 	%f730, 0f3DAAAABD;
+	mov.f32 	%f729, 0f3C4CAF63;
+	mov.f32 	%f728, 0f3B18F0FE;
+	mov.f32 	%f727, 0f3EE66666;
+	setp.eq.f32	%p77, %f70, 0f3F800000;
+	selp.f32	%f102, 0f3F800000, %f789, %p77;
+	abs.f32 	%f103, %f71;
+	setp.lt.f32	%p78, %f103, 0f00800000;
+	mul.f32 	%f476, %f103, 0f4B800000;
+	selp.f32	%f477, 0fC3170000, 0fC2FE0000, %p78;
+	selp.f32	%f478, %f476, %f103, %p78;
+	mov.b32 	 %r253, %f478;
+	and.b32  	%r254, %r253, 8388607;
+	or.b32  	%r255, %r254, 1065353216;
+	mov.b32 	 %f479, %r255;
+	shr.u32 	%r256, %r253, 23;
+	cvt.rn.f32.u32	%f480, %r256;
+	add.f32 	%f481, %f477, %f480;
+	setp.gt.f32	%p79, %f479, 0f3FB504F3;
+	mul.f32 	%f482, %f479, 0f3F000000;
+	add.f32 	%f483, %f481, 0f3F800000;
+	selp.f32	%f484, %f482, %f479, %p79;
+	selp.f32	%f485, %f483, %f481, %p79;
+	add.f32 	%f486, %f484, 0fBF800000;
+	add.f32 	%f475, %f484, 0f3F800000;
+	// inline asm
+	rcp.approx.ftz.f32 %f474,%f475;
+	// inline asm
+	add.f32 	%f487, %f486, %f486;
+	mul.f32 	%f488, %f474, %f487;
+	mul.f32 	%f489, %f488, %f488;
+	fma.rn.f32 	%f492, %f728, %f489, %f729;
+	fma.rn.f32 	%f494, %f492, %f489, %f730;
+	mul.rn.f32 	%f495, %f494, %f489;
+	mul.rn.f32 	%f496, %f495, %f488;
+	sub.f32 	%f497, %f486, %f488;
+	neg.f32 	%f498, %f488;
+	add.f32 	%f499, %f497, %f497;
+	fma.rn.f32 	%f500, %f498, %f486, %f499;
+	mul.rn.f32 	%f501, %f474, %f500;
+	add.f32 	%f502, %f496, %f488;
+	sub.f32 	%f503, %f488, %f502;
+	add.f32 	%f504, %f496, %f503;
+	add.f32 	%f505, %f501, %f504;
+	add.f32 	%f506, %f502, %f505;
+	sub.f32 	%f507, %f502, %f506;
+	add.f32 	%f508, %f505, %f507;
+	mul.rn.f32 	%f510, %f485, %f731;
+	mul.rn.f32 	%f512, %f485, %f732;
+	add.f32 	%f513, %f510, %f506;
+	sub.f32 	%f514, %f510, %f513;
+	add.f32 	%f515, %f506, %f514;
+	add.f32 	%f516, %f508, %f515;
+	add.f32 	%f517, %f512, %f516;
+	add.f32 	%f518, %f513, %f517;
+	sub.f32 	%f519, %f513, %f518;
+	add.f32 	%f520, %f517, %f519;
+	mul.rn.f32 	%f522, %f727, %f518;
+	neg.f32 	%f523, %f522;
+	fma.rn.f32 	%f524, %f727, %f518, %f523;
+	fma.rn.f32 	%f525, %f727, %f520, %f524;
+	fma.rn.f32 	%f527, %f733, %f518, %f525;
+	add.rn.f32 	%f528, %f522, %f527;
+	neg.f32 	%f529, %f528;
+	add.rn.f32 	%f530, %f522, %f529;
+	add.rn.f32 	%f531, %f530, %f527;
+	mov.b32 	 %r257, %f528;
+	setp.eq.s32	%p80, %r257, 1118925336;
+	add.s32 	%r258, %r257, -1;
+	mov.b32 	 %f532, %r258;
+	add.f32 	%f533, %f531, 0f37000000;
+	selp.f32	%f534, %f532, %f528, %p80;
+	selp.f32	%f104, %f533, %f531, %p80;
+	mul.f32 	%f535, %f534, 0f3FB8AA3B;
+	cvt.rzi.f32.f32	%f536, %f535;
+	fma.rn.f32 	%f538, %f536, %f734, %f534;
+	fma.rn.f32 	%f540, %f536, %f735, %f538;
+	mul.f32 	%f541, %f540, 0f3FB8AA3B;
+	ex2.approx.ftz.f32 	%f542, %f541;
+	add.f32 	%f543, %f536, 0f00000000;
+	ex2.approx.f32 	%f544, %f543;
+	mul.f32 	%f545, %f542, %f544;
+	setp.lt.f32	%p81, %f534, 0fC2D20000;
+	selp.f32	%f546, 0f00000000, %f545, %p81;
+	setp.gt.f32	%p82, %f534, 0f42D20000;
+	selp.f32	%f790, 0f7F800000, %f546, %p82;
+	setp.eq.f32	%p83, %f790, 0f7F800000;
+	@%p83 bra 	BB0_84;
+
+	fma.rn.f32 	%f790, %f790, %f104, %f790;
+
+BB0_84:
+	setp.lt.f32	%p84, %f71, 0f00000000;
+	and.pred  	%p3, %p84, %p69;
+	mov.b32 	 %r259, %f790;
+	xor.b32  	%r260, %r259, -2147483648;
+	mov.b32 	 %f547, %r260;
+	selp.f32	%f792, %f547, %f790, %p3;
+	setp.eq.f32	%p86, %f71, 0f00000000;
+	@%p86 bra 	BB0_87;
+	bra.uni 	BB0_85;
+
+BB0_87:
+	add.f32 	%f550, %f71, %f71;
+	selp.f32	%f792, %f550, 0f00000000, %p69;
+	bra.uni 	BB0_88;
+
+BB0_85:
+	setp.geu.f32	%p87, %f71, 0f00000000;
+	@%p87 bra 	BB0_88;
+
+	mov.f32 	%f746, 0f3EE66666;
+	cvt.rzi.f32.f32	%f549, %f746;
+	setp.neu.f32	%p88, %f549, 0f3EE66666;
+	selp.f32	%f792, 0f7FFFFFFF, %f792, %p88;
+
+BB0_88:
+	abs.f32 	%f750, %f71;
+	add.f32 	%f551, %f750, 0f3EE66666;
+	mov.b32 	 %r261, %f551;
+	setp.lt.s32	%p90, %r261, 2139095040;
+	@%p90 bra 	BB0_93;
+
+	abs.f32 	%f751, %f71;
+	setp.gtu.f32	%p91, %f751, 0f7F800000;
+	@%p91 bra 	BB0_92;
+	bra.uni 	BB0_90;
+
+BB0_92:
+	add.f32 	%f792, %f71, 0f3EE66666;
+	bra.uni 	BB0_93;
+
+BB0_90:
+	abs.f32 	%f752, %f71;
+	setp.neu.f32	%p92, %f752, 0f7F800000;
+	@%p92 bra 	BB0_93;
+
+	selp.f32	%f792, 0fFF800000, 0f7F800000, %p3;
+
+BB0_93:
+	mov.f32 	%f744, 0fB5BFBE8E;
+	mov.f32 	%f743, 0fBF317200;
+	mov.f32 	%f742, 0f00000000;
+	mov.f32 	%f741, 0f35BFBE8E;
+	mov.f32 	%f740, 0f3F317200;
+	mov.f32 	%f739, 0f3DAAAABD;
+	mov.f32 	%f738, 0f3C4CAF63;
+	mov.f32 	%f737, 0f3B18F0FE;
+	mov.f32 	%f736, 0f3EE66666;
+	setp.eq.f32	%p93, %f71, 0f3F800000;
+	selp.f32	%f115, 0f3F800000, %f792, %p93;
+	abs.f32 	%f116, %f72;
+	setp.lt.f32	%p94, %f116, 0f00800000;
+	mul.f32 	%f554, %f116, 0f4B800000;
+	selp.f32	%f555, 0fC3170000, 0fC2FE0000, %p94;
+	selp.f32	%f556, %f554, %f116, %p94;
+	mov.b32 	 %r262, %f556;
+	and.b32  	%r263, %r262, 8388607;
+	or.b32  	%r264, %r263, 1065353216;
+	mov.b32 	 %f557, %r264;
+	shr.u32 	%r265, %r262, 23;
+	cvt.rn.f32.u32	%f558, %r265;
+	add.f32 	%f559, %f555, %f558;
+	setp.gt.f32	%p95, %f557, 0f3FB504F3;
+	mul.f32 	%f560, %f557, 0f3F000000;
+	add.f32 	%f561, %f559, 0f3F800000;
+	selp.f32	%f562, %f560, %f557, %p95;
+	selp.f32	%f563, %f561, %f559, %p95;
+	add.f32 	%f564, %f562, 0fBF800000;
+	add.f32 	%f553, %f562, 0f3F800000;
+	// inline asm
+	rcp.approx.ftz.f32 %f552,%f553;
+	// inline asm
+	add.f32 	%f565, %f564, %f564;
+	mul.f32 	%f566, %f552, %f565;
+	mul.f32 	%f567, %f566, %f566;
+	fma.rn.f32 	%f570, %f737, %f567, %f738;
+	fma.rn.f32 	%f572, %f570, %f567, %f739;
+	mul.rn.f32 	%f573, %f572, %f567;
+	mul.rn.f32 	%f574, %f573, %f566;
+	sub.f32 	%f575, %f564, %f566;
+	neg.f32 	%f576, %f566;
+	add.f32 	%f577, %f575, %f575;
+	fma.rn.f32 	%f578, %f576, %f564, %f577;
+	mul.rn.f32 	%f579, %f552, %f578;
+	add.f32 	%f580, %f574, %f566;
+	sub.f32 	%f581, %f566, %f580;
+	add.f32 	%f582, %f574, %f581;
+	add.f32 	%f583, %f579, %f582;
+	add.f32 	%f584, %f580, %f583;
+	sub.f32 	%f585, %f580, %f584;
+	add.f32 	%f586, %f583, %f585;
+	mul.rn.f32 	%f588, %f563, %f740;
+	mul.rn.f32 	%f590, %f563, %f741;
+	add.f32 	%f591, %f588, %f584;
+	sub.f32 	%f592, %f588, %f591;
+	add.f32 	%f593, %f584, %f592;
+	add.f32 	%f594, %f586, %f593;
+	add.f32 	%f595, %f590, %f594;
+	add.f32 	%f596, %f591, %f595;
+	sub.f32 	%f597, %f591, %f596;
+	add.f32 	%f598, %f595, %f597;
+	mul.rn.f32 	%f600, %f736, %f596;
+	neg.f32 	%f601, %f600;
+	fma.rn.f32 	%f602, %f736, %f596, %f601;
+	fma.rn.f32 	%f603, %f736, %f598, %f602;
+	fma.rn.f32 	%f605, %f742, %f596, %f603;
+	add.rn.f32 	%f606, %f600, %f605;
+	neg.f32 	%f607, %f606;
+	add.rn.f32 	%f608, %f600, %f607;
+	add.rn.f32 	%f609, %f608, %f605;
+	mov.b32 	 %r266, %f606;
+	setp.eq.s32	%p96, %r266, 1118925336;
+	add.s32 	%r267, %r266, -1;
+	mov.b32 	 %f610, %r267;
+	add.f32 	%f611, %f609, 0f37000000;
+	selp.f32	%f612, %f610, %f606, %p96;
+	selp.f32	%f117, %f611, %f609, %p96;
+	mul.f32 	%f613, %f612, 0f3FB8AA3B;
+	cvt.rzi.f32.f32	%f614, %f613;
+	fma.rn.f32 	%f616, %f614, %f743, %f612;
+	fma.rn.f32 	%f618, %f614, %f744, %f616;
+	mul.f32 	%f619, %f618, 0f3FB8AA3B;
+	ex2.approx.ftz.f32 	%f620, %f619;
+	add.f32 	%f621, %f614, 0f00000000;
+	ex2.approx.f32 	%f622, %f621;
+	mul.f32 	%f623, %f620, %f622;
+	setp.lt.f32	%p97, %f612, 0fC2D20000;
+	selp.f32	%f624, 0f00000000, %f623, %p97;
+	setp.gt.f32	%p98, %f612, 0f42D20000;
+	selp.f32	%f793, 0f7F800000, %f624, %p98;
+	setp.eq.f32	%p99, %f793, 0f7F800000;
+	@%p99 bra 	BB0_95;
+
+	fma.rn.f32 	%f793, %f793, %f117, %f793;
+
+BB0_95:
+	setp.lt.f32	%p100, %f72, 0f00000000;
+	and.pred  	%p4, %p100, %p69;
+	mov.b32 	 %r268, %f793;
+	xor.b32  	%r269, %r268, -2147483648;
+	mov.b32 	 %f625, %r269;
+	selp.f32	%f795, %f625, %f793, %p4;
+	setp.eq.f32	%p102, %f72, 0f00000000;
+	@%p102 bra 	BB0_98;
+	bra.uni 	BB0_96;
+
+BB0_98:
+	add.f32 	%f628, %f72, %f72;
+	selp.f32	%f795, %f628, 0f00000000, %p69;
+	bra.uni 	BB0_99;
+
+BB0_96:
+	setp.geu.f32	%p103, %f72, 0f00000000;
+	@%p103 bra 	BB0_99;
+
+	mov.f32 	%f745, 0f3EE66666;
+	cvt.rzi.f32.f32	%f627, %f745;
+	setp.neu.f32	%p104, %f627, 0f3EE66666;
+	selp.f32	%f795, 0f7FFFFFFF, %f795, %p104;
+
+BB0_99:
+	abs.f32 	%f761, %f72;
+	add.f32 	%f629, %f761, 0f3EE66666;
+	mov.b32 	 %r270, %f629;
+	setp.lt.s32	%p106, %r270, 2139095040;
+	@%p106 bra 	BB0_104;
+
+	abs.f32 	%f762, %f72;
+	setp.gtu.f32	%p107, %f762, 0f7F800000;
+	@%p107 bra 	BB0_103;
+	bra.uni 	BB0_101;
+
+BB0_103:
+	add.f32 	%f795, %f72, 0f3EE66666;
+	bra.uni 	BB0_104;
+
+BB0_101:
+	abs.f32 	%f763, %f72;
+	setp.neu.f32	%p108, %f763, 0f7F800000;
+	@%p108 bra 	BB0_104;
+
+	selp.f32	%f795, 0fFF800000, 0f7F800000, %p4;
+
+BB0_104:
+	mov.u32 	%r355, 4;
+	setp.eq.f32	%p109, %f72, 0f3F800000;
+	selp.f32	%f630, 0f3F800000, %f795, %p109;
+	cvt.u64.u32	%rd63, %r3;
+	cvt.u64.u32	%rd62, %r2;
+	mov.u64 	%rd66, image;
+	cvta.global.u64 	%rd61, %rd66;
+	// inline asm
+	call (%rd60), _rt_buffer_get_64, (%rd61, %r99, %r355, %rd62, %rd63, %rd25, %rd25);
+	// inline asm
+	cvt.sat.f32.f32	%f631, %f630;
+	mul.f32 	%f632, %f631, 0f437FFD71;
+	cvt.rzi.u32.f32	%r273, %f632;
+	cvt.sat.f32.f32	%f633, %f115;
+	mul.f32 	%f634, %f633, 0f437FFD71;
+	cvt.rzi.u32.f32	%r274, %f634;
+	cvt.sat.f32.f32	%f635, %f102;
+	mul.f32 	%f636, %f635, 0f437FFD71;
+	cvt.rzi.u32.f32	%r275, %f636;
+	cvt.u16.u32	%rs16, %r273;
+	cvt.u16.u32	%rs17, %r275;
+	cvt.u16.u32	%rs18, %r274;
+	mov.u16 	%rs19, 255;
+	st.v4.u8 	[%rd60], {%rs16, %rs18, %rs17, %rs19};
+	ld.global.u32 	%r385, [imageEnabled];
+
+BB0_105:
+	cvt.u64.u32	%rd16, %r2;
+	cvt.u64.u32	%rd17, %r3;
+	and.b32  	%r276, %r385, 4;
+	setp.eq.s32	%p110, %r276, 0;
+	@%p110 bra 	BB0_109;
+
+	ld.global.u32 	%r277, [additive];
+	setp.eq.s32	%p111, %r277, 0;
+	mov.f32 	%f637, 0f3F800000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs20, %f637;}
+
+	// inline asm
+	@%p111 bra 	BB0_108;
+
+	mov.u64 	%rd79, image_HDR;
+	cvta.global.u64 	%rd68, %rd79;
+	mov.u32 	%r281, 8;
+	// inline asm
+	call (%rd67), _rt_buffer_get_64, (%rd68, %r99, %r281, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	ld.v4.u16 	{%rs27, %rs28, %rs29, %rs30}, [%rd67];
+	// inline asm
+	{  cvt.f32.f16 %f638, %rs27;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f639, %rs28;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f640, %rs29;}
+
+	// inline asm
+	// inline asm
+	call (%rd73), _rt_buffer_get_64, (%rd68, %r99, %r281, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	add.f32 	%f641, %f70, %f638;
+	add.f32 	%f642, %f71, %f639;
+	add.f32 	%f643, %f72, %f640;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs26, %f643;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs25, %f642;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs24, %f641;}
+
+	// inline asm
+	st.v4.u16 	[%rd73], {%rs24, %rs25, %rs26, %rs20};
+	bra.uni 	BB0_109;
+
+BB0_108:
+	mov.u64 	%rd86, image_HDR;
+	cvta.global.u64 	%rd81, %rd86;
+	mov.u32 	%r283, 8;
+	// inline asm
+	call (%rd80), _rt_buffer_get_64, (%rd81, %r99, %r283, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs33, %f72;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs32, %f71;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs31, %f70;}
+
+	// inline asm
+	st.v4.u16 	[%rd80], {%rs31, %rs32, %rs33, %rs20};
+
+BB0_109:
+	ld.global.u32 	%r284, [additive];
+	setp.eq.s32	%p112, %r284, 0;
+	mov.f32 	%f647, 0f3F800000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs34, %f647;}
+
+	// inline asm
+	@%p112 bra 	BB0_111;
+
+	mov.u64 	%rd99, image_RNM0;
+	cvta.global.u64 	%rd88, %rd99;
+	mov.u32 	%r288, 8;
+	// inline asm
+	call (%rd87), _rt_buffer_get_64, (%rd88, %r99, %r288, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	ld.v4.u16 	{%rs41, %rs42, %rs43, %rs44}, [%rd87];
+	// inline asm
+	{  cvt.f32.f16 %f648, %rs41;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f649, %rs42;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f650, %rs43;}
+
+	// inline asm
+	// inline asm
+	call (%rd93), _rt_buffer_get_64, (%rd88, %r99, %r288, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	add.f32 	%f651, %f73, %f648;
+	add.f32 	%f652, %f74, %f649;
+	add.f32 	%f653, %f75, %f650;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs40, %f653;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs39, %f652;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs38, %f651;}
+
+	// inline asm
+	st.v4.u16 	[%rd93], {%rs38, %rs39, %rs40, %rs34};
+	bra.uni 	BB0_112;
+
+BB0_111:
+	mov.u64 	%rd106, image_RNM0;
+	cvta.global.u64 	%rd101, %rd106;
+	mov.u32 	%r290, 8;
+	// inline asm
+	call (%rd100), _rt_buffer_get_64, (%rd101, %r99, %r290, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs47, %f75;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs46, %f74;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs45, %f73;}
+
+	// inline asm
+	st.v4.u16 	[%rd100], {%rs45, %rs46, %rs47, %rs34};
+
+BB0_112:
+	ld.global.f32 	%f658, [directDir];
+	fma.rn.f32 	%f128, %f658, 0fBF000000, 0f3F000000;
+	ld.global.f32 	%f659, [directDir+4];
+	fma.rn.f32 	%f129, %f659, 0fBF000000, 0f3F000000;
+	ld.global.f32 	%f660, [directDir+8];
+	fma.rn.f32 	%f130, %f660, 0fBF000000, 0f3F000000;
+	ld.global.u32 	%r291, [additive];
+	setp.eq.s32	%p113, %r291, 0;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs48, %f647;}
+
+	// inline asm
+	@%p113 bra 	BB0_114;
+
+	mov.u64 	%rd119, image_RNM1;
+	cvta.global.u64 	%rd108, %rd119;
+	mov.u32 	%r295, 8;
+	// inline asm
+	call (%rd107), _rt_buffer_get_64, (%rd108, %r99, %r295, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	ld.v4.u16 	{%rs55, %rs56, %rs57, %rs58}, [%rd107];
+	// inline asm
+	{  cvt.f32.f16 %f661, %rs55;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f662, %rs56;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f663, %rs57;}
+
+	// inline asm
+	// inline asm
+	call (%rd113), _rt_buffer_get_64, (%rd108, %r99, %r295, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	add.f32 	%f664, %f128, %f661;
+	add.f32 	%f665, %f128, %f662;
+	add.f32 	%f666, %f128, %f663;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs54, %f666;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs53, %f665;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs52, %f664;}
+
+	// inline asm
+	st.v4.u16 	[%rd113], {%rs52, %rs53, %rs54, %rs48};
+	bra.uni 	BB0_115;
+
+BB0_114:
+	mov.u64 	%rd126, image_RNM1;
+	cvta.global.u64 	%rd121, %rd126;
+	mov.u32 	%r297, 8;
+	// inline asm
+	call (%rd120), _rt_buffer_get_64, (%rd121, %r99, %r297, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs59, %f128;}
+
+	// inline asm
+	st.v4.u16 	[%rd120], {%rs59, %rs59, %rs59, %rs48};
+
+BB0_115:
+	ld.global.u32 	%r298, [additive];
+	setp.eq.s32	%p114, %r298, 0;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs60, %f647;}
+
+	// inline asm
+	@%p114 bra 	BB0_117;
+
+	mov.u64 	%rd139, image_RNM2;
+	cvta.global.u64 	%rd128, %rd139;
+	mov.u32 	%r302, 8;
+	// inline asm
+	call (%rd127), _rt_buffer_get_64, (%rd128, %r99, %r302, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	ld.v4.u16 	{%rs67, %rs68, %rs69, %rs70}, [%rd127];
+	// inline asm
+	{  cvt.f32.f16 %f669, %rs67;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f670, %rs68;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f671, %rs69;}
+
+	// inline asm
+	// inline asm
+	call (%rd133), _rt_buffer_get_64, (%rd128, %r99, %r302, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	add.f32 	%f672, %f129, %f669;
+	add.f32 	%f673, %f129, %f670;
+	add.f32 	%f674, %f129, %f671;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs66, %f674;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs65, %f673;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs64, %f672;}
+
+	// inline asm
+	st.v4.u16 	[%rd133], {%rs64, %rs65, %rs66, %rs60};
+	bra.uni 	BB0_118;
+
+BB0_117:
+	mov.u64 	%rd146, image_RNM2;
+	cvta.global.u64 	%rd141, %rd146;
+	mov.u32 	%r304, 8;
+	// inline asm
+	call (%rd140), _rt_buffer_get_64, (%rd141, %r99, %r304, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs71, %f129;}
+
+	// inline asm
+	st.v4.u16 	[%rd140], {%rs71, %rs71, %rs71, %rs60};
+
+BB0_118:
+	ld.global.u32 	%r305, [additive];
+	setp.eq.s32	%p115, %r305, 0;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs72, %f647;}
+
+	// inline asm
+	@%p115 bra 	BB0_120;
+
+	mov.u64 	%rd159, image_RNM3;
+	cvta.global.u64 	%rd148, %rd159;
+	mov.u32 	%r309, 8;
+	// inline asm
+	call (%rd147), _rt_buffer_get_64, (%rd148, %r99, %r309, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	ld.v4.u16 	{%rs79, %rs80, %rs81, %rs82}, [%rd147];
+	// inline asm
+	{  cvt.f32.f16 %f677, %rs79;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f678, %rs80;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f679, %rs81;}
+
+	// inline asm
+	// inline asm
+	call (%rd153), _rt_buffer_get_64, (%rd148, %r99, %r309, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	add.f32 	%f680, %f130, %f677;
+	add.f32 	%f681, %f130, %f678;
+	add.f32 	%f682, %f130, %f679;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs78, %f682;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs77, %f681;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs76, %f680;}
+
+	// inline asm
+	st.v4.u16 	[%rd153], {%rs76, %rs77, %rs78, %rs72};
+	bra.uni 	BB0_141;
+
+BB0_120:
+	mov.u64 	%rd166, image_RNM3;
+	cvta.global.u64 	%rd161, %rd166;
+	mov.u32 	%r311, 8;
+	// inline asm
+	call (%rd160), _rt_buffer_get_64, (%rd161, %r99, %r311, %rd16, %rd17, %rd25, %rd25);
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs83, %f130;}
+
+	// inline asm
+	st.v4.u16 	[%rd160], {%rs83, %rs83, %rs83, %rs72};
+
+BB0_141:
+	ret;
+}
+
+