move to self host

1 files changed, 2403 insertions, 0 deletions

diff --git a/VRCSDK3Worlds/Assets/Editor/x64/Bakery/lmSunRNM.ptx b/VRCSDK3Worlds/Assets/Editor/x64/Bakery/lmSunRNM.ptx
new file mode 100644
index 00000000..c3c59af8
--- /dev/null
+++ b/VRCSDK3Worlds/Assets/Editor/x64/Bakery/lmSunRNM.ptx
@@ -0,0 +1,2403 @@
+//
+// Generated by NVIDIA NVVM Compiler
+//
+// Compiler Build ID: CL-23083092
+// Cuda compilation tools, release 9.1, V9.1.85
+// Based on LLVM 3.4svn
+//
+
+.version 6.1
+.target sm_30
+.address_size 64
+
+	// .globl	_Z6oxMainv
+.global .align 8 .b8 pixelID[8];
+.global .align 8 .b8 resolution[8];
+.global .align 4 .b8 normal[12];
+.global .align 4 .b8 camPos[12];
+.global .align 4 .b8 root[4];
+.global .align 4 .u32 imageEnabled;
+.global .texref lightmap;
+.global .align 16 .b8 tileInfo[16];
+.global .align 4 .u32 additive;
+.global .align 1 .b8 image[1];
+.global .align 1 .b8 image_HDR[1];
+.global .align 1 .b8 image_HDR2[1];
+.global .align 1 .b8 image_Mask[1];
+.global .align 1 .b8 image_RNM0[1];
+.global .align 1 .b8 image_RNM1[1];
+.global .align 1 .b8 image_RNM2[1];
+.global .align 1 .b8 uvtangent[1];
+.global .align 1 .b8 uvpos[1];
+.global .align 1 .b8 uvnormal[1];
+.global .align 1 .b8 rnd_seeds[1];
+.global .align 4 .b8 directDir[12];
+.global .align 4 .b8 directColor[12];
+.global .align 4 .f32 shadowSpread;
+.global .align 4 .u32 samples;
+.global .align 4 .u32 ignoreNormal;
+.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo6normalE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo6camPosE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo4rootE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo12imageEnabledE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo8tileInfoE[8] = {82, 97, 121, 0, 16, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo8additiveE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo9directDirE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo11directColorE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo12shadowSpreadE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo7samplesE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo12ignoreNormalE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E;
+.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE;
+.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE;
+.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE;
+.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename6normalE[7] = {102, 108, 111, 97, 116, 51, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename6camPosE[7] = {102, 108, 111, 97, 116, 51, 0};
+.global .align 16 .b8 _ZN21rti_internal_typename4rootE[9] = {114, 116, 79, 98, 106, 101, 99, 116, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename12imageEnabledE[4] = {105, 110, 116, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename8tileInfoE[6] = {117, 105, 110, 116, 52, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename8additiveE[4] = {105, 110, 116, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename9directDirE[7] = {102, 108, 111, 97, 116, 51, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename11directColorE[7] = {102, 108, 111, 97, 116, 51, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename12shadowSpreadE[6] = {102, 108, 111, 97, 116, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename7samplesE[4] = {105, 110, 116, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename12ignoreNormalE[4] = {105, 110, 116, 0};
+.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum6normalE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum6camPosE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum4rootE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum12imageEnabledE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum8tileInfoE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum8additiveE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum9directDirE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum11directColorE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum12shadowSpreadE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum7samplesE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum12ignoreNormalE = 4919;
+.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0};
+.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0};
+.global .align 16 .b8 _ZN21rti_internal_semantic6normalE[17] = {97, 116, 116, 114, 105, 98, 117, 116, 101, 32, 110, 111, 114, 109, 97, 108, 0};
+.global .align 1 .b8 _ZN21rti_internal_semantic6camPosE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic4rootE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic12imageEnabledE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic8tileInfoE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic8additiveE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic9directDirE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic11directColorE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic12shadowSpreadE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic7samplesE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic12ignoreNormalE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation6normalE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation6camPosE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation4rootE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation12imageEnabledE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation8tileInfoE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation8additiveE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation9directDirE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation11directColorE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation12shadowSpreadE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation7samplesE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation12ignoreNormalE[1];
+.const .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
+
+.visible .entry _Z6oxMainv(
+
+)
+{
+	.local .align 4 .b8 	__local_depot0[32];
+	.reg .b64 	%SP;
+	.reg .b64 	%SPL;
+	.reg .pred 	%p<148>;
+	.reg .b16 	%rs<157>;
+	.reg .f32 	%f<1107>;
+	.reg .b32 	%r<410>;
+	.reg .b64 	%rd<272>;
+
+
+	mov.u64 	%rd271, __local_depot0;
+	cvta.local.u64 	%SP, %rd271;
+	ld.global.v2.u32 	{%r107, %r108}, [pixelID];
+	cvt.u64.u32	%rd27, %r107;
+	cvt.u64.u32	%rd28, %r108;
+	mov.u64 	%rd31, uvnormal;
+	cvta.global.u64 	%rd26, %rd31;
+	mov.u32 	%r105, 2;
+	mov.u32 	%r106, 4;
+	mov.u64 	%rd30, 0;
+	// inline asm
+	call (%rd25), _rt_buffer_get_64, (%rd26, %r105, %r106, %rd27, %rd28, %rd30, %rd30);
+	// inline asm
+	ld.u32 	%r1, [%rd25];
+	shr.u32 	%r111, %r1, 16;
+	cvt.u16.u32	%rs1, %r111;
+	and.b16  	%rs6, %rs1, 255;
+	cvt.u16.u32	%rs7, %r1;
+	or.b16  	%rs8, %rs7, %rs6;
+	setp.eq.s16	%p6, %rs8, 0;
+	mov.f32 	%f1063, 0f00000000;
+	mov.f32 	%f1064, %f1063;
+	mov.f32 	%f1065, %f1063;
+	@%p6 bra 	BB0_2;
+
+	ld.u8 	%rs9, [%rd25+1];
+	and.b16  	%rs11, %rs7, 255;
+	cvt.rn.f32.u16	%f184, %rs11;
+	div.rn.f32 	%f185, %f184, 0f437F0000;
+	fma.rn.f32 	%f186, %f185, 0f40000000, 0fBF800000;
+	cvt.rn.f32.u16	%f187, %rs9;
+	div.rn.f32 	%f188, %f187, 0f437F0000;
+	fma.rn.f32 	%f189, %f188, 0f40000000, 0fBF800000;
+	cvt.rn.f32.u16	%f190, %rs6;
+	div.rn.f32 	%f191, %f190, 0f437F0000;
+	fma.rn.f32 	%f192, %f191, 0f40000000, 0fBF800000;
+	mul.f32 	%f193, %f189, %f189;
+	fma.rn.f32 	%f194, %f186, %f186, %f193;
+	fma.rn.f32 	%f195, %f192, %f192, %f194;
+	sqrt.rn.f32 	%f196, %f195;
+	rcp.rn.f32 	%f197, %f196;
+	mul.f32 	%f1063, %f186, %f197;
+	mul.f32 	%f1064, %f189, %f197;
+	mul.f32 	%f1065, %f192, %f197;
+
+BB0_2:
+	ld.global.v2.u32 	{%r112, %r113}, [pixelID];
+	ld.global.v2.u32 	{%r115, %r116}, [tileInfo];
+	add.s32 	%r2, %r112, %r115;
+	add.s32 	%r3, %r113, %r116;
+	setp.eq.f32	%p7, %f1064, 0f00000000;
+	setp.eq.f32	%p8, %f1063, 0f00000000;
+	and.pred  	%p9, %p8, %p7;
+	setp.eq.f32	%p10, %f1065, 0f00000000;
+	and.pred  	%p11, %p9, %p10;
+	@%p11 bra 	BB0_135;
+	bra.uni 	BB0_3;
+
+BB0_135:
+	ld.global.u32 	%r409, [imageEnabled];
+	and.b32  	%r338, %r409, 1;
+	setp.eq.b32	%p141, %r338, 1;
+	@!%p141 bra 	BB0_137;
+	bra.uni 	BB0_136;
+
+BB0_136:
+	cvt.u64.u32	%rd175, %r2;
+	cvt.u64.u32	%rd176, %r3;
+	mov.u64 	%rd179, image;
+	cvta.global.u64 	%rd174, %rd179;
+	// inline asm
+	call (%rd173), _rt_buffer_get_64, (%rd174, %r105, %r106, %rd175, %rd176, %rd30, %rd30);
+	// inline asm
+	mov.u16 	%rs102, 0;
+	st.v4.u8 	[%rd173], {%rs102, %rs102, %rs102, %rs102};
+	ld.global.u32 	%r409, [imageEnabled];
+
+BB0_137:
+	and.b32  	%r341, %r409, 8;
+	setp.eq.s32	%p142, %r341, 0;
+	@%p142 bra 	BB0_139;
+
+	cvt.u64.u32	%rd183, %r3;
+	cvt.u64.u32	%rd182, %r2;
+	mov.u64 	%rd186, image_Mask;
+	cvta.global.u64 	%rd181, %rd186;
+	// inline asm
+	call (%rd180), _rt_buffer_get_64, (%rd181, %r105, %r105, %rd182, %rd183, %rd30, %rd30);
+	// inline asm
+	mov.f32 	%f966, 0f00000000;
+	cvt.rzi.u32.f32	%r344, %f966;
+	cvt.u16.u32	%rs103, %r344;
+	mov.u16 	%rs104, 0;
+	st.v2.u8 	[%rd180], {%rs103, %rs104};
+	ld.global.u32 	%r409, [imageEnabled];
+
+BB0_139:
+	cvt.u64.u32	%rd23, %r2;
+	cvt.u64.u32	%rd24, %r3;
+	and.b32  	%r345, %r409, 4;
+	setp.eq.s32	%p143, %r345, 0;
+	@%p143 bra 	BB0_143;
+
+	ld.global.u32 	%r346, [additive];
+	setp.eq.s32	%p144, %r346, 0;
+	@%p144 bra 	BB0_142;
+
+	mov.u64 	%rd199, image_HDR;
+	cvta.global.u64 	%rd188, %rd199;
+	mov.u32 	%r350, 8;
+	// inline asm
+	call (%rd187), _rt_buffer_get_64, (%rd188, %r105, %r350, %rd23, %rd24, %rd30, %rd30);
+	// inline asm
+	ld.v4.u16 	{%rs111, %rs112, %rs113, %rs114}, [%rd187];
+	// inline asm
+	{  cvt.f32.f16 %f967, %rs111;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f968, %rs112;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f969, %rs113;}
+
+	// inline asm
+	// inline asm
+	call (%rd193), _rt_buffer_get_64, (%rd188, %r105, %r350, %rd23, %rd24, %rd30, %rd30);
+	// inline asm
+	add.f32 	%f970, %f967, 0f00000000;
+	add.f32 	%f971, %f968, 0f00000000;
+	add.f32 	%f972, %f969, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs110, %f972;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs109, %f971;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs108, %f970;}
+
+	// inline asm
+	mov.u16 	%rs115, 0;
+	st.v4.u16 	[%rd193], {%rs108, %rs109, %rs110, %rs115};
+	bra.uni 	BB0_143;
+
+BB0_3:
+	ld.global.f32 	%f8, [directDir+4];
+	ld.global.f32 	%f9, [directDir+8];
+	ld.global.f32 	%f7, [directDir];
+	ld.global.v2.u32 	{%r124, %r125}, [pixelID];
+	cvt.u64.u32	%rd34, %r124;
+	cvt.u64.u32	%rd35, %r125;
+	mov.u64 	%rd44, uvpos;
+	cvta.global.u64 	%rd33, %rd44;
+	mov.u32 	%r121, 12;
+	// inline asm
+	call (%rd32), _rt_buffer_get_64, (%rd33, %r105, %r121, %rd34, %rd35, %rd30, %rd30);
+	// inline asm
+	ld.f32 	%f199, [%rd32+8];
+	ld.f32 	%f200, [%rd32+4];
+	ld.f32 	%f201, [%rd32];
+	mul.f32 	%f202, %f201, 0f3456BF95;
+	mul.f32 	%f203, %f200, 0f3456BF95;
+	mul.f32 	%f204, %f199, 0f3456BF95;
+	abs.f32 	%f205, %f1063;
+	div.rn.f32 	%f206, %f202, %f205;
+	abs.f32 	%f207, %f1064;
+	div.rn.f32 	%f208, %f203, %f207;
+	abs.f32 	%f209, %f1065;
+	div.rn.f32 	%f210, %f204, %f209;
+	abs.f32 	%f211, %f206;
+	abs.f32 	%f212, %f208;
+	abs.f32 	%f213, %f210;
+	mov.f32 	%f214, 0f38D1B717;
+	max.f32 	%f215, %f211, %f214;
+	max.f32 	%f216, %f212, %f214;
+	max.f32 	%f217, %f213, %f214;
+	fma.rn.f32 	%f10, %f1063, %f215, %f201;
+	fma.rn.f32 	%f11, %f1064, %f216, %f200;
+	fma.rn.f32 	%f12, %f1065, %f217, %f199;
+	abs.f32 	%f218, %f7;
+	abs.f32 	%f219, %f9;
+	setp.gt.f32	%p12, %f218, %f219;
+	neg.f32 	%f220, %f8;
+	neg.f32 	%f221, %f9;
+	selp.f32	%f222, %f220, 0f00000000, %p12;
+	selp.f32	%f223, %f7, %f221, %p12;
+	selp.f32	%f224, 0f00000000, %f8, %p12;
+	mul.f32 	%f225, %f223, %f223;
+	fma.rn.f32 	%f226, %f222, %f222, %f225;
+	fma.rn.f32 	%f227, %f224, %f224, %f226;
+	sqrt.rn.f32 	%f228, %f227;
+	rcp.rn.f32 	%f229, %f228;
+	mul.f32 	%f13, %f222, %f229;
+	mul.f32 	%f14, %f223, %f229;
+	mul.f32 	%f15, %f224, %f229;
+	ld.global.v2.u32 	{%r128, %r129}, [pixelID];
+	cvt.u64.u32	%rd40, %r128;
+	cvt.u64.u32	%rd41, %r129;
+	mov.u64 	%rd45, rnd_seeds;
+	cvta.global.u64 	%rd39, %rd45;
+	// inline asm
+	call (%rd38), _rt_buffer_get_64, (%rd39, %r105, %r106, %rd40, %rd41, %rd30, %rd30);
+	// inline asm
+	ld.global.u32 	%r378, [samples];
+	mov.f32 	%f1080, 0f00000000;
+	setp.lt.s32	%p13, %r378, 1;
+	@%p13 bra 	BB0_55;
+
+	cvt.rn.f32.s32	%f231, %r378;
+	rcp.rn.f32 	%f16, %f231;
+	ld.u32 	%r404, [%rd38];
+	mul.f32 	%f17, %f10, 0f3456BF95;
+	mul.f32 	%f18, %f11, 0f3456BF95;
+	mul.f32 	%f19, %f12, 0f3456BF95;
+	mul.f32 	%f232, %f7, %f14;
+	mul.f32 	%f233, %f8, %f13;
+	sub.f32 	%f20, %f233, %f232;
+	mul.f32 	%f234, %f9, %f13;
+	mul.f32 	%f235, %f7, %f15;
+	sub.f32 	%f21, %f235, %f234;
+	mul.f32 	%f236, %f8, %f15;
+	mul.f32 	%f237, %f9, %f14;
+	sub.f32 	%f22, %f237, %f236;
+	mov.f32 	%f1080, 0f00000000;
+	mov.u32 	%r379, 0;
+	abs.f32 	%f238, %f18;
+	abs.f32 	%f239, %f17;
+	max.f32 	%f240, %f239, %f238;
+	abs.f32 	%f241, %f19;
+	max.f32 	%f242, %f240, %f241;
+
+BB0_5:
+	setp.lt.s32	%p14, %r378, 1;
+	@%p14 bra 	BB0_54;
+
+	cvt.rn.f32.s32	%f24, %r379;
+	max.f32 	%f25, %f242, %f214;
+	mov.u32 	%r381, 0;
+
+BB0_7:
+	mad.lo.s32 	%r134, %r404, 1664525, 1013904223;
+	and.b32  	%r135, %r134, 16777215;
+	cvt.rn.f32.u32	%f244, %r135;
+	fma.rn.f32 	%f245, %f244, 0f33800000, %f24;
+	mul.f32 	%f246, %f16, %f245;
+	mad.lo.s32 	%r404, %r134, 1664525, 1013904223;
+	and.b32  	%r136, %r404, 16777215;
+	cvt.rn.f32.u32	%f247, %r136;
+	cvt.rn.f32.s32	%f248, %r381;
+	fma.rn.f32 	%f249, %f247, 0f33800000, %f248;
+	mul.f32 	%f250, %f16, %f249;
+	sqrt.rn.f32 	%f27, %f246;
+	mul.f32 	%f1074, %f250, 0f40C90FDB;
+	abs.f32 	%f29, %f1074;
+	setp.neu.f32	%p15, %f29, 0f7F800000;
+	mov.f32 	%f1068, %f1074;
+	@%p15 bra 	BB0_9;
+
+	mov.f32 	%f251, 0f00000000;
+	mul.rn.f32 	%f1068, %f1074, %f251;
+
+BB0_9:
+	mul.f32 	%f252, %f1068, 0f3F22F983;
+	cvt.rni.s32.f32	%r392, %f252;
+	cvt.rn.f32.s32	%f253, %r392;
+	neg.f32 	%f254, %f253;
+	mov.f32 	%f255, 0f3FC90FDA;
+	fma.rn.f32 	%f256, %f254, %f255, %f1068;
+	mov.f32 	%f257, 0f33A22168;
+	fma.rn.f32 	%f258, %f254, %f257, %f256;
+	mov.f32 	%f259, 0f27C234C5;
+	fma.rn.f32 	%f1069, %f254, %f259, %f258;
+	abs.f32 	%f260, %f1068;
+	setp.leu.f32	%p16, %f260, 0f47CE4780;
+	@%p16 bra 	BB0_20;
+
+	mov.b32 	 %r13, %f1068;
+	shr.u32 	%r14, %r13, 23;
+	shl.b32 	%r139, %r13, 8;
+	or.b32  	%r15, %r139, -2147483648;
+	add.u64 	%rd47, %SP, 4;
+	cvta.to.local.u64 	%rd268, %rd47;
+	mov.u32 	%r384, 0;
+	mov.u64 	%rd267, __cudart_i2opi_f;
+	mov.u32 	%r383, -6;
+
+BB0_11:
+	.pragma "nounroll";
+	ld.const.u32 	%r142, [%rd267];
+	// inline asm
+	{
+	mad.lo.cc.u32   %r140, %r142, %r15, %r384;
+	madc.hi.u32     %r384, %r142, %r15,  0;
+	}
+	// inline asm
+	st.local.u32 	[%rd268], %r140;
+	add.s64 	%rd268, %rd268, 4;
+	add.s64 	%rd267, %rd267, 4;
+	add.s32 	%r383, %r383, 1;
+	setp.ne.s32	%p17, %r383, 0;
+	@%p17 bra 	BB0_11;
+
+	and.b32  	%r145, %r14, 255;
+	add.s32 	%r146, %r145, -128;
+	shr.u32 	%r147, %r146, 5;
+	and.b32  	%r20, %r13, -2147483648;
+	cvta.to.local.u64 	%rd49, %rd47;
+	st.local.u32 	[%rd49+24], %r384;
+	mov.u32 	%r148, 6;
+	sub.s32 	%r149, %r148, %r147;
+	mul.wide.s32 	%rd50, %r149, 4;
+	add.s64 	%rd8, %rd49, %rd50;
+	ld.local.u32 	%r385, [%rd8];
+	ld.local.u32 	%r386, [%rd8+-4];
+	and.b32  	%r23, %r14, 31;
+	setp.eq.s32	%p18, %r23, 0;
+	@%p18 bra 	BB0_14;
+
+	mov.u32 	%r150, 32;
+	sub.s32 	%r151, %r150, %r23;
+	shr.u32 	%r152, %r386, %r151;
+	shl.b32 	%r153, %r385, %r23;
+	add.s32 	%r385, %r152, %r153;
+	ld.local.u32 	%r154, [%rd8+-8];
+	shr.u32 	%r155, %r154, %r151;
+	shl.b32 	%r156, %r386, %r23;
+	add.s32 	%r386, %r155, %r156;
+
+BB0_14:
+	shr.u32 	%r157, %r386, 30;
+	shl.b32 	%r158, %r385, 2;
+	add.s32 	%r387, %r157, %r158;
+	shl.b32 	%r29, %r386, 2;
+	shr.u32 	%r159, %r387, 31;
+	shr.u32 	%r160, %r385, 30;
+	add.s32 	%r30, %r159, %r160;
+	setp.eq.s32	%p19, %r159, 0;
+	@%p19 bra 	BB0_15;
+	bra.uni 	BB0_16;
+
+BB0_15:
+	mov.u32 	%r388, %r20;
+	mov.u32 	%r389, %r29;
+	bra.uni 	BB0_17;
+
+BB0_16:
+	not.b32 	%r161, %r387;
+	neg.s32 	%r389, %r29;
+	setp.eq.s32	%p20, %r29, 0;
+	selp.u32	%r162, 1, 0, %p20;
+	add.s32 	%r387, %r162, %r161;
+	xor.b32  	%r388, %r20, -2147483648;
+
+BB0_17:
+	clz.b32 	%r391, %r387;
+	setp.eq.s32	%p21, %r391, 0;
+	shl.b32 	%r163, %r387, %r391;
+	mov.u32 	%r164, 32;
+	sub.s32 	%r165, %r164, %r391;
+	shr.u32 	%r166, %r389, %r165;
+	add.s32 	%r167, %r166, %r163;
+	selp.b32	%r38, %r387, %r167, %p21;
+	mov.u32 	%r168, -921707870;
+	mul.hi.u32 	%r390, %r38, %r168;
+	setp.eq.s32	%p22, %r20, 0;
+	neg.s32 	%r169, %r30;
+	selp.b32	%r392, %r30, %r169, %p22;
+	setp.lt.s32	%p23, %r390, 1;
+	@%p23 bra 	BB0_19;
+
+	mul.lo.s32 	%r170, %r38, -921707870;
+	shr.u32 	%r171, %r170, 31;
+	shl.b32 	%r172, %r390, 1;
+	add.s32 	%r390, %r171, %r172;
+	add.s32 	%r391, %r391, 1;
+
+BB0_19:
+	mov.u32 	%r173, 126;
+	sub.s32 	%r174, %r173, %r391;
+	shl.b32 	%r175, %r174, 23;
+	add.s32 	%r176, %r390, 1;
+	shr.u32 	%r177, %r176, 7;
+	add.s32 	%r178, %r177, 1;
+	shr.u32 	%r179, %r178, 1;
+	add.s32 	%r180, %r179, %r175;
+	or.b32  	%r181, %r180, %r388;
+	mov.b32 	 %f1069, %r181;
+
+BB0_20:
+	mul.rn.f32 	%f35, %f1069, %f1069;
+	add.s32 	%r46, %r392, 1;
+	and.b32  	%r47, %r46, 1;
+	setp.eq.s32	%p24, %r47, 0;
+	@%p24 bra 	BB0_22;
+	bra.uni 	BB0_21;
+
+BB0_22:
+	mov.f32 	%f263, 0f3C08839E;
+	mov.f32 	%f264, 0fB94CA1F9;
+	fma.rn.f32 	%f1070, %f264, %f35, %f263;
+	bra.uni 	BB0_23;
+
+BB0_21:
+	mov.f32 	%f261, 0fBAB6061A;
+	mov.f32 	%f262, 0f37CCF5CE;
+	fma.rn.f32 	%f1070, %f262, %f35, %f261;
+
+BB0_23:
+	@%p24 bra 	BB0_25;
+	bra.uni 	BB0_24;
+
+BB0_25:
+	mov.f32 	%f268, 0fBE2AAAA3;
+	fma.rn.f32 	%f269, %f1070, %f35, %f268;
+	mov.f32 	%f270, 0f00000000;
+	fma.rn.f32 	%f1071, %f269, %f35, %f270;
+	bra.uni 	BB0_26;
+
+BB0_24:
+	mov.f32 	%f265, 0f3D2AAAA5;
+	fma.rn.f32 	%f266, %f1070, %f35, %f265;
+	mov.f32 	%f267, 0fBF000000;
+	fma.rn.f32 	%f1071, %f266, %f35, %f267;
+
+BB0_26:
+	fma.rn.f32 	%f1072, %f1071, %f1069, %f1069;
+	@%p24 bra 	BB0_28;
+
+	mov.f32 	%f271, 0f3F800000;
+	fma.rn.f32 	%f1072, %f1071, %f35, %f271;
+
+BB0_28:
+	and.b32  	%r182, %r46, 2;
+	setp.eq.s32	%p27, %r182, 0;
+	@%p27 bra 	BB0_30;
+
+	mov.f32 	%f272, 0f00000000;
+	mov.f32 	%f273, 0fBF800000;
+	fma.rn.f32 	%f1072, %f1072, %f273, %f272;
+
+BB0_30:
+	@%p15 bra 	BB0_32;
+
+	mov.f32 	%f274, 0f00000000;
+	mul.rn.f32 	%f1074, %f1074, %f274;
+
+BB0_32:
+	mul.f32 	%f275, %f1074, 0f3F22F983;
+	cvt.rni.s32.f32	%r402, %f275;
+	cvt.rn.f32.s32	%f276, %r402;
+	neg.f32 	%f277, %f276;
+	fma.rn.f32 	%f279, %f277, %f255, %f1074;
+	fma.rn.f32 	%f281, %f277, %f257, %f279;
+	fma.rn.f32 	%f1075, %f277, %f259, %f281;
+	abs.f32 	%f283, %f1074;
+	setp.leu.f32	%p29, %f283, 0f47CE4780;
+	@%p29 bra 	BB0_43;
+
+	mov.b32 	 %r49, %f1074;
+	shr.u32 	%r50, %r49, 23;
+	shl.b32 	%r185, %r49, 8;
+	or.b32  	%r51, %r185, -2147483648;
+	add.u64 	%rd52, %SP, 4;
+	cvta.to.local.u64 	%rd270, %rd52;
+	mov.u32 	%r394, 0;
+	mov.u64 	%rd269, __cudart_i2opi_f;
+	mov.u32 	%r393, -6;
+
+BB0_34:
+	.pragma "nounroll";
+	ld.const.u32 	%r188, [%rd269];
+	// inline asm
+	{
+	mad.lo.cc.u32   %r186, %r188, %r51, %r394;
+	madc.hi.u32     %r394, %r188, %r51,  0;
+	}
+	// inline asm
+	st.local.u32 	[%rd270], %r186;
+	add.s64 	%rd270, %rd270, 4;
+	add.s64 	%rd269, %rd269, 4;
+	add.s32 	%r393, %r393, 1;
+	setp.ne.s32	%p30, %r393, 0;
+	@%p30 bra 	BB0_34;
+
+	and.b32  	%r191, %r50, 255;
+	add.s32 	%r192, %r191, -128;
+	shr.u32 	%r193, %r192, 5;
+	and.b32  	%r56, %r49, -2147483648;
+	cvta.to.local.u64 	%rd54, %rd52;
+	st.local.u32 	[%rd54+24], %r394;
+	mov.u32 	%r194, 6;
+	sub.s32 	%r195, %r194, %r193;
+	mul.wide.s32 	%rd55, %r195, 4;
+	add.s64 	%rd14, %rd54, %rd55;
+	ld.local.u32 	%r395, [%rd14];
+	ld.local.u32 	%r396, [%rd14+-4];
+	and.b32  	%r59, %r50, 31;
+	setp.eq.s32	%p31, %r59, 0;
+	@%p31 bra 	BB0_37;
+
+	mov.u32 	%r196, 32;
+	sub.s32 	%r197, %r196, %r59;
+	shr.u32 	%r198, %r396, %r197;
+	shl.b32 	%r199, %r395, %r59;
+	add.s32 	%r395, %r198, %r199;
+	ld.local.u32 	%r200, [%rd14+-8];
+	shr.u32 	%r201, %r200, %r197;
+	shl.b32 	%r202, %r396, %r59;
+	add.s32 	%r396, %r201, %r202;
+
+BB0_37:
+	shr.u32 	%r203, %r396, 30;
+	shl.b32 	%r204, %r395, 2;
+	add.s32 	%r397, %r203, %r204;
+	shl.b32 	%r65, %r396, 2;
+	shr.u32 	%r205, %r397, 31;
+	shr.u32 	%r206, %r395, 30;
+	add.s32 	%r66, %r205, %r206;
+	setp.eq.s32	%p32, %r205, 0;
+	@%p32 bra 	BB0_38;
+	bra.uni 	BB0_39;
+
+BB0_38:
+	mov.u32 	%r398, %r56;
+	mov.u32 	%r399, %r65;
+	bra.uni 	BB0_40;
+
+BB0_39:
+	not.b32 	%r207, %r397;
+	neg.s32 	%r399, %r65;
+	setp.eq.s32	%p33, %r65, 0;
+	selp.u32	%r208, 1, 0, %p33;
+	add.s32 	%r397, %r208, %r207;
+	xor.b32  	%r398, %r56, -2147483648;
+
+BB0_40:
+	clz.b32 	%r401, %r397;
+	setp.eq.s32	%p34, %r401, 0;
+	shl.b32 	%r209, %r397, %r401;
+	mov.u32 	%r210, 32;
+	sub.s32 	%r211, %r210, %r401;
+	shr.u32 	%r212, %r399, %r211;
+	add.s32 	%r213, %r212, %r209;
+	selp.b32	%r74, %r397, %r213, %p34;
+	mov.u32 	%r214, -921707870;
+	mul.hi.u32 	%r400, %r74, %r214;
+	setp.eq.s32	%p35, %r56, 0;
+	neg.s32 	%r215, %r66;
+	selp.b32	%r402, %r66, %r215, %p35;
+	setp.lt.s32	%p36, %r400, 1;
+	@%p36 bra 	BB0_42;
+
+	mul.lo.s32 	%r216, %r74, -921707870;
+	shr.u32 	%r217, %r216, 31;
+	shl.b32 	%r218, %r400, 1;
+	add.s32 	%r400, %r217, %r218;
+	add.s32 	%r401, %r401, 1;
+
+BB0_42:
+	mov.u32 	%r219, 126;
+	sub.s32 	%r220, %r219, %r401;
+	shl.b32 	%r221, %r220, 23;
+	add.s32 	%r222, %r400, 1;
+	shr.u32 	%r223, %r222, 7;
+	add.s32 	%r224, %r223, 1;
+	shr.u32 	%r225, %r224, 1;
+	add.s32 	%r226, %r225, %r221;
+	or.b32  	%r227, %r226, %r398;
+	mov.b32 	 %f1075, %r227;
+
+BB0_43:
+	mul.rn.f32 	%f52, %f1075, %f1075;
+	and.b32  	%r82, %r402, 1;
+	setp.eq.s32	%p37, %r82, 0;
+	@%p37 bra 	BB0_45;
+	bra.uni 	BB0_44;
+
+BB0_45:
+	mov.f32 	%f286, 0f3C08839E;
+	mov.f32 	%f287, 0fB94CA1F9;
+	fma.rn.f32 	%f1076, %f287, %f52, %f286;
+	bra.uni 	BB0_46;
+
+BB0_44:
+	mov.f32 	%f284, 0fBAB6061A;
+	mov.f32 	%f285, 0f37CCF5CE;
+	fma.rn.f32 	%f1076, %f285, %f52, %f284;
+
+BB0_46:
+	@%p37 bra 	BB0_48;
+	bra.uni 	BB0_47;
+
+BB0_48:
+	mov.f32 	%f291, 0fBE2AAAA3;
+	fma.rn.f32 	%f292, %f1076, %f52, %f291;
+	mov.f32 	%f293, 0f00000000;
+	fma.rn.f32 	%f1077, %f292, %f52, %f293;
+	bra.uni 	BB0_49;
+
+BB0_47:
+	mov.f32 	%f288, 0f3D2AAAA5;
+	fma.rn.f32 	%f289, %f1076, %f52, %f288;
+	mov.f32 	%f290, 0fBF000000;
+	fma.rn.f32 	%f1077, %f289, %f52, %f290;
+
+BB0_49:
+	fma.rn.f32 	%f1078, %f1077, %f1075, %f1075;
+	@%p37 bra 	BB0_51;
+
+	mov.f32 	%f294, 0f3F800000;
+	fma.rn.f32 	%f1078, %f1077, %f52, %f294;
+
+BB0_51:
+	and.b32  	%r228, %r402, 2;
+	setp.eq.s32	%p40, %r228, 0;
+	@%p40 bra 	BB0_53;
+
+	mov.f32 	%f295, 0f00000000;
+	mov.f32 	%f296, 0fBF800000;
+	fma.rn.f32 	%f1078, %f1078, %f296, %f295;
+
+BB0_53:
+	mul.f32 	%f305, %f27, %f1072;
+	add.u64 	%rd56, %SP, 0;
+	cvta.to.local.u64 	%rd57, %rd56;
+	mul.f32 	%f306, %f305, %f305;
+	mov.f32 	%f307, 0f3F800000;
+	sub.f32 	%f308, %f307, %f306;
+	mul.f32 	%f309, %f27, %f1078;
+	mul.f32 	%f310, %f309, %f309;
+	sub.f32 	%f311, %f308, %f310;
+	mov.f32 	%f312, 0f00000000;
+	max.f32 	%f313, %f312, %f311;
+	sqrt.rn.f32 	%f314, %f313;
+	mul.f32 	%f315, %f13, %f309;
+	mul.f32 	%f316, %f14, %f309;
+	mul.f32 	%f317, %f15, %f309;
+	fma.rn.f32 	%f318, %f22, %f305, %f315;
+	fma.rn.f32 	%f319, %f21, %f305, %f316;
+	fma.rn.f32 	%f320, %f20, %f305, %f317;
+	fma.rn.f32 	%f321, %f7, %f314, %f318;
+	fma.rn.f32 	%f322, %f8, %f314, %f319;
+	fma.rn.f32 	%f323, %f9, %f314, %f320;
+	add.f32 	%f324, %f7, %f321;
+	add.f32 	%f325, %f8, %f322;
+	add.f32 	%f326, %f9, %f323;
+	ld.global.f32 	%f327, [shadowSpread];
+	mul.f32 	%f328, %f327, %f324;
+	mul.f32 	%f329, %f327, %f325;
+	mul.f32 	%f330, %f327, %f326;
+	sub.f32 	%f331, %f328, %f7;
+	sub.f32 	%f332, %f329, %f8;
+	sub.f32 	%f333, %f330, %f9;
+	mul.f32 	%f334, %f332, %f332;
+	fma.rn.f32 	%f335, %f331, %f331, %f334;
+	fma.rn.f32 	%f336, %f333, %f333, %f335;
+	sqrt.rn.f32 	%f337, %f336;
+	rcp.rn.f32 	%f338, %f337;
+	mul.f32 	%f300, %f338, %f331;
+	mul.f32 	%f301, %f338, %f332;
+	mul.f32 	%f302, %f338, %f333;
+	ld.global.u32 	%r232, [imageEnabled];
+	and.b32  	%r233, %r232, 32;
+	setp.eq.s32	%p41, %r233, 0;
+	selp.f32	%f339, 0f3F800000, 0f41200000, %p41;
+	mul.f32 	%f303, %f339, %f25;
+	mov.u32 	%r234, 1065353216;
+	st.local.u32 	[%rd57], %r234;
+	ld.global.u32 	%r229, [root];
+	mov.u32 	%r230, 1;
+	mov.f32 	%f304, 0f6C4ECB8F;
+	// inline asm
+	call _rt_trace_64, (%r229, %f10, %f11, %f12, %f300, %f301, %f302, %r230, %f303, %f304, %rd56, %r106);
+	// inline asm
+	ld.local.f32 	%f340, [%rd57];
+	add.f32 	%f1080, %f1080, %f340;
+	ld.global.u32 	%r378, [samples];
+	add.s32 	%r381, %r381, 1;
+	setp.lt.s32	%p42, %r381, %r378;
+	@%p42 bra 	BB0_7;
+
+BB0_54:
+	add.s32 	%r379, %r379, 1;
+	setp.lt.s32	%p43, %r379, %r378;
+	@%p43 bra 	BB0_5;
+
+BB0_55:
+	mul.f32 	%f342, %f1065, %f9;
+	mul.f32 	%f343, %f1064, %f8;
+	neg.f32 	%f344, %f343;
+	mul.f32 	%f345, %f1063, %f7;
+	sub.f32 	%f346, %f344, %f345;
+	sub.f32 	%f67, %f346, %f342;
+	setp.eq.s32	%p44, %r378, 0;
+	mov.f32 	%f1082, 0f3F800000;
+	@%p44 bra 	BB0_57;
+
+	mul.lo.s32 	%r235, %r378, %r378;
+	cvt.rn.f32.s32	%f347, %r235;
+	div.rn.f32 	%f1082, %f1080, %f347;
+
+BB0_57:
+	ld.global.f32 	%f350, [directColor];
+	mul.f32 	%f70, %f1082, %f350;
+	ld.global.f32 	%f351, [directColor+4];
+	mul.f32 	%f71, %f1082, %f351;
+	ld.global.f32 	%f352, [directColor+8];
+	mul.f32 	%f72, %f1082, %f352;
+	cvt.sat.f32.f32	%f353, %f67;
+	mul.f32 	%f73, %f70, %f353;
+	mul.f32 	%f74, %f71, %f353;
+	mul.f32 	%f75, %f72, %f353;
+	fma.rn.f32 	%f354, %f67, 0f3F000000, 0f3F000000;
+	cvt.sat.f32.f32	%f355, %f354;
+	add.f32 	%f76, %f355, %f355;
+	mov.f32 	%f359, 0f41A00000;
+	abs.f32 	%f78, %f76;
+	setp.lt.f32	%p45, %f78, 0f00800000;
+	mul.f32 	%f361, %f78, 0f4B800000;
+	selp.f32	%f362, 0fC3170000, 0fC2FE0000, %p45;
+	selp.f32	%f363, %f361, %f78, %p45;
+	mov.b32 	 %r236, %f363;
+	and.b32  	%r237, %r236, 8388607;
+	or.b32  	%r238, %r237, 1065353216;
+	mov.b32 	 %f364, %r238;
+	shr.u32 	%r239, %r236, 23;
+	cvt.rn.f32.u32	%f365, %r239;
+	add.f32 	%f366, %f362, %f365;
+	setp.gt.f32	%p46, %f364, 0f3FB504F3;
+	mul.f32 	%f367, %f364, 0f3F000000;
+	add.f32 	%f368, %f366, 0f3F800000;
+	selp.f32	%f369, %f367, %f364, %p46;
+	selp.f32	%f370, %f368, %f366, %p46;
+	add.f32 	%f371, %f369, 0fBF800000;
+	add.f32 	%f349, %f369, 0f3F800000;
+	// inline asm
+	rcp.approx.ftz.f32 %f348,%f349;
+	// inline asm
+	add.f32 	%f372, %f371, %f371;
+	mul.f32 	%f373, %f348, %f372;
+	mul.f32 	%f374, %f373, %f373;
+	mov.f32 	%f375, 0f3C4CAF63;
+	mov.f32 	%f376, 0f3B18F0FE;
+	fma.rn.f32 	%f377, %f376, %f374, %f375;
+	mov.f32 	%f378, 0f3DAAAABD;
+	fma.rn.f32 	%f379, %f377, %f374, %f378;
+	mul.rn.f32 	%f380, %f379, %f374;
+	mul.rn.f32 	%f381, %f380, %f373;
+	sub.f32 	%f382, %f371, %f373;
+	neg.f32 	%f383, %f373;
+	add.f32 	%f384, %f382, %f382;
+	fma.rn.f32 	%f385, %f383, %f371, %f384;
+	mul.rn.f32 	%f386, %f348, %f385;
+	add.f32 	%f387, %f381, %f373;
+	sub.f32 	%f388, %f373, %f387;
+	add.f32 	%f389, %f381, %f388;
+	add.f32 	%f390, %f386, %f389;
+	add.f32 	%f391, %f387, %f390;
+	sub.f32 	%f392, %f387, %f391;
+	add.f32 	%f393, %f390, %f392;
+	mov.f32 	%f394, 0f3F317200;
+	mul.rn.f32 	%f395, %f370, %f394;
+	mov.f32 	%f396, 0f35BFBE8E;
+	mul.rn.f32 	%f397, %f370, %f396;
+	add.f32 	%f398, %f395, %f391;
+	sub.f32 	%f399, %f395, %f398;
+	add.f32 	%f400, %f391, %f399;
+	add.f32 	%f401, %f393, %f400;
+	add.f32 	%f402, %f397, %f401;
+	add.f32 	%f403, %f398, %f402;
+	sub.f32 	%f404, %f398, %f403;
+	add.f32 	%f405, %f402, %f404;
+	mul.rn.f32 	%f406, %f359, %f403;
+	neg.f32 	%f407, %f406;
+	fma.rn.f32 	%f408, %f359, %f403, %f407;
+	fma.rn.f32 	%f409, %f359, %f405, %f408;
+	mov.f32 	%f410, 0f00000000;
+	fma.rn.f32 	%f411, %f410, %f403, %f409;
+	add.rn.f32 	%f412, %f406, %f411;
+	neg.f32 	%f413, %f412;
+	add.rn.f32 	%f414, %f406, %f413;
+	add.rn.f32 	%f415, %f414, %f411;
+	mov.b32 	 %r240, %f412;
+	setp.eq.s32	%p47, %r240, 1118925336;
+	add.s32 	%r241, %r240, -1;
+	mov.b32 	 %f416, %r241;
+	add.f32 	%f417, %f415, 0f37000000;
+	selp.f32	%f418, %f416, %f412, %p47;
+	selp.f32	%f79, %f417, %f415, %p47;
+	mul.f32 	%f419, %f418, 0f3FB8AA3B;
+	cvt.rzi.f32.f32	%f420, %f419;
+	mov.f32 	%f421, 0fBF317200;
+	fma.rn.f32 	%f422, %f420, %f421, %f418;
+	mov.f32 	%f423, 0fB5BFBE8E;
+	fma.rn.f32 	%f424, %f420, %f423, %f422;
+	mul.f32 	%f425, %f424, 0f3FB8AA3B;
+	ex2.approx.ftz.f32 	%f426, %f425;
+	add.f32 	%f427, %f420, 0f00000000;
+	ex2.approx.f32 	%f428, %f427;
+	mul.f32 	%f429, %f426, %f428;
+	setp.lt.f32	%p48, %f418, 0fC2D20000;
+	selp.f32	%f430, 0f00000000, %f429, %p48;
+	setp.gt.f32	%p49, %f418, 0f42D20000;
+	selp.f32	%f1083, 0f7F800000, %f430, %p49;
+	setp.eq.f32	%p50, %f1083, 0f7F800000;
+	@%p50 bra 	BB0_59;
+
+	fma.rn.f32 	%f1083, %f1083, %f79, %f1083;
+
+BB0_59:
+	mov.f32 	%f1000, 0f41200000;
+	cvt.rzi.f32.f32	%f999, %f1000;
+	add.f32 	%f998, %f999, %f999;
+	mov.f32 	%f997, 0f41A00000;
+	sub.f32 	%f996, %f997, %f998;
+	abs.f32 	%f995, %f996;
+	setp.lt.f32	%p51, %f76, 0f00000000;
+	setp.eq.f32	%p52, %f995, 0f3F800000;
+	and.pred  	%p1, %p51, %p52;
+	mov.b32 	 %r242, %f1083;
+	xor.b32  	%r243, %r242, -2147483648;
+	mov.b32 	 %f431, %r243;
+	selp.f32	%f1085, %f431, %f1083, %p1;
+	setp.eq.f32	%p53, %f76, 0f00000000;
+	@%p53 bra 	BB0_62;
+	bra.uni 	BB0_60;
+
+BB0_62:
+	add.f32 	%f434, %f76, %f76;
+	selp.f32	%f1085, %f434, 0f00000000, %p52;
+	bra.uni 	BB0_63;
+
+BB0_60:
+	setp.geu.f32	%p54, %f76, 0f00000000;
+	@%p54 bra 	BB0_63;
+
+	mov.f32 	%f1036, 0f41A00000;
+	cvt.rzi.f32.f32	%f433, %f1036;
+	setp.neu.f32	%p55, %f433, 0f41A00000;
+	selp.f32	%f1085, 0f7FFFFFFF, %f1085, %p55;
+
+BB0_63:
+	add.f32 	%f435, %f78, 0f41A00000;
+	mov.b32 	 %r244, %f435;
+	setp.lt.s32	%p57, %r244, 2139095040;
+	@%p57 bra 	BB0_68;
+
+	setp.gtu.f32	%p58, %f78, 0f7F800000;
+	@%p58 bra 	BB0_67;
+	bra.uni 	BB0_65;
+
+BB0_67:
+	add.f32 	%f1085, %f76, 0f41A00000;
+	bra.uni 	BB0_68;
+
+BB0_65:
+	setp.neu.f32	%p59, %f78, 0f7F800000;
+	@%p59 bra 	BB0_68;
+
+	selp.f32	%f1085, 0fFF800000, 0f7F800000, %p1;
+
+BB0_68:
+	setp.eq.f32	%p60, %f76, 0f3F800000;
+	selp.f32	%f436, 0f3F800000, %f1085, %p60;
+	cvt.sat.f32.f32	%f437, %f436;
+	mul.f32 	%f90, %f70, %f437;
+	mul.f32 	%f91, %f71, %f437;
+	mul.f32 	%f92, %f72, %f437;
+	ld.global.u32 	%r407, [imageEnabled];
+	and.b32  	%r245, %r407, 8;
+	setp.eq.s32	%p61, %r245, 0;
+	@%p61 bra 	BB0_81;
+
+	mov.f32 	%f1008, 0fB5BFBE8E;
+	mov.f32 	%f1007, 0fBF317200;
+	mov.f32 	%f1006, 0f00000000;
+	mov.f32 	%f1005, 0f35BFBE8E;
+	mov.f32 	%f1004, 0f3F317200;
+	mov.f32 	%f1003, 0f3DAAAABD;
+	mov.f32 	%f1002, 0f3C4CAF63;
+	mov.f32 	%f1001, 0f3B18F0FE;
+	cvt.u64.u32	%rd60, %r2;
+	cvt.u64.u32	%rd61, %r3;
+	mov.u64 	%rd64, image_Mask;
+	cvta.global.u64 	%rd59, %rd64;
+	// inline asm
+	call (%rd58), _rt_buffer_get_64, (%rd59, %r105, %r105, %rd60, %rd61, %rd30, %rd30);
+	// inline asm
+	abs.f32 	%f94, %f1082;
+	setp.lt.f32	%p62, %f94, 0f00800000;
+	mul.f32 	%f443, %f94, 0f4B800000;
+	selp.f32	%f444, 0fC3170000, 0fC2FE0000, %p62;
+	selp.f32	%f445, %f443, %f94, %p62;
+	mov.b32 	 %r248, %f445;
+	and.b32  	%r249, %r248, 8388607;
+	or.b32  	%r250, %r249, 1065353216;
+	mov.b32 	 %f446, %r250;
+	shr.u32 	%r251, %r248, 23;
+	cvt.rn.f32.u32	%f447, %r251;
+	add.f32 	%f448, %f444, %f447;
+	setp.gt.f32	%p63, %f446, 0f3FB504F3;
+	mul.f32 	%f449, %f446, 0f3F000000;
+	add.f32 	%f450, %f448, 0f3F800000;
+	selp.f32	%f451, %f449, %f446, %p63;
+	selp.f32	%f452, %f450, %f448, %p63;
+	add.f32 	%f453, %f451, 0fBF800000;
+	add.f32 	%f439, %f451, 0f3F800000;
+	// inline asm
+	rcp.approx.ftz.f32 %f438,%f439;
+	// inline asm
+	add.f32 	%f454, %f453, %f453;
+	mul.f32 	%f455, %f438, %f454;
+	mul.f32 	%f456, %f455, %f455;
+	fma.rn.f32 	%f459, %f1001, %f456, %f1002;
+	fma.rn.f32 	%f461, %f459, %f456, %f1003;
+	mul.rn.f32 	%f462, %f461, %f456;
+	mul.rn.f32 	%f463, %f462, %f455;
+	sub.f32 	%f464, %f453, %f455;
+	neg.f32 	%f465, %f455;
+	add.f32 	%f466, %f464, %f464;
+	fma.rn.f32 	%f467, %f465, %f453, %f466;
+	mul.rn.f32 	%f468, %f438, %f467;
+	add.f32 	%f469, %f463, %f455;
+	sub.f32 	%f470, %f455, %f469;
+	add.f32 	%f471, %f463, %f470;
+	add.f32 	%f472, %f468, %f471;
+	add.f32 	%f473, %f469, %f472;
+	sub.f32 	%f474, %f469, %f473;
+	add.f32 	%f475, %f472, %f474;
+	mul.rn.f32 	%f477, %f452, %f1004;
+	mul.rn.f32 	%f479, %f452, %f1005;
+	add.f32 	%f480, %f477, %f473;
+	sub.f32 	%f481, %f477, %f480;
+	add.f32 	%f482, %f473, %f481;
+	add.f32 	%f483, %f475, %f482;
+	add.f32 	%f484, %f479, %f483;
+	add.f32 	%f485, %f480, %f484;
+	sub.f32 	%f486, %f480, %f485;
+	add.f32 	%f487, %f484, %f486;
+	mov.f32 	%f488, 0f3EE8BA2E;
+	mul.rn.f32 	%f489, %f488, %f485;
+	neg.f32 	%f490, %f489;
+	fma.rn.f32 	%f491, %f488, %f485, %f490;
+	fma.rn.f32 	%f492, %f488, %f487, %f491;
+	fma.rn.f32 	%f494, %f1006, %f485, %f492;
+	add.rn.f32 	%f495, %f489, %f494;
+	neg.f32 	%f496, %f495;
+	add.rn.f32 	%f497, %f489, %f496;
+	add.rn.f32 	%f498, %f497, %f494;
+	mov.b32 	 %r252, %f495;
+	setp.eq.s32	%p64, %r252, 1118925336;
+	add.s32 	%r253, %r252, -1;
+	mov.b32 	 %f499, %r253;
+	add.f32 	%f500, %f498, 0f37000000;
+	selp.f32	%f501, %f499, %f495, %p64;
+	selp.f32	%f95, %f500, %f498, %p64;
+	mul.f32 	%f502, %f501, 0f3FB8AA3B;
+	cvt.rzi.f32.f32	%f503, %f502;
+	fma.rn.f32 	%f505, %f503, %f1007, %f501;
+	fma.rn.f32 	%f507, %f503, %f1008, %f505;
+	mul.f32 	%f508, %f507, 0f3FB8AA3B;
+	ex2.approx.ftz.f32 	%f509, %f508;
+	add.f32 	%f510, %f503, 0f00000000;
+	ex2.approx.f32 	%f511, %f510;
+	mul.f32 	%f512, %f509, %f511;
+	setp.lt.f32	%p65, %f501, 0fC2D20000;
+	selp.f32	%f513, 0f00000000, %f512, %p65;
+	setp.gt.f32	%p66, %f501, 0f42D20000;
+	selp.f32	%f1086, 0f7F800000, %f513, %p66;
+	setp.eq.f32	%p67, %f1086, 0f7F800000;
+	@%p67 bra 	BB0_71;
+
+	fma.rn.f32 	%f1086, %f1086, %f95, %f1086;
+
+BB0_71:
+	mov.f32 	%f1040, 0f3E68BA2E;
+	cvt.rzi.f32.f32	%f1039, %f1040;
+	fma.rn.f32 	%f1038, %f1039, 0fC0000000, 0f3EE8BA2E;
+	abs.f32 	%f1037, %f1038;
+	setp.lt.f32	%p68, %f1082, 0f00000000;
+	setp.eq.f32	%p69, %f1037, 0f3F800000;
+	and.pred  	%p2, %p68, %p69;
+	mov.b32 	 %r254, %f1086;
+	xor.b32  	%r255, %r254, -2147483648;
+	mov.b32 	 %f514, %r255;
+	selp.f32	%f1088, %f514, %f1086, %p2;
+	setp.eq.f32	%p70, %f1082, 0f00000000;
+	@%p70 bra 	BB0_74;
+	bra.uni 	BB0_72;
+
+BB0_74:
+	add.f32 	%f517, %f1082, %f1082;
+	selp.f32	%f1088, %f517, 0f00000000, %p69;
+	bra.uni 	BB0_75;
+
+BB0_142:
+	mov.u64 	%rd206, image_HDR;
+	cvta.global.u64 	%rd201, %rd206;
+	mov.u32 	%r352, 8;
+	// inline asm
+	call (%rd200), _rt_buffer_get_64, (%rd201, %r105, %r352, %rd23, %rd24, %rd30, %rd30);
+	// inline asm
+	mov.f32 	%f973, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs116, %f973;}
+
+	// inline asm
+	mov.u16 	%rs117, 0;
+	st.v4.u16 	[%rd200], {%rs116, %rs116, %rs116, %rs117};
+
+BB0_143:
+	ld.global.u32 	%r353, [additive];
+	setp.eq.s32	%p145, %r353, 0;
+	@%p145 bra 	BB0_145;
+
+	mov.u64 	%rd219, image_RNM0;
+	cvta.global.u64 	%rd208, %rd219;
+	mov.u32 	%r357, 8;
+	// inline asm
+	call (%rd207), _rt_buffer_get_64, (%rd208, %r105, %r357, %rd23, %rd24, %rd30, %rd30);
+	// inline asm
+	ld.v4.u16 	{%rs124, %rs125, %rs126, %rs127}, [%rd207];
+	// inline asm
+	{  cvt.f32.f16 %f974, %rs124;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f975, %rs125;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f976, %rs126;}
+
+	// inline asm
+	// inline asm
+	call (%rd213), _rt_buffer_get_64, (%rd208, %r105, %r357, %rd23, %rd24, %rd30, %rd30);
+	// inline asm
+	add.f32 	%f977, %f974, 0f00000000;
+	add.f32 	%f978, %f975, 0f00000000;
+	add.f32 	%f979, %f976, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs123, %f979;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs122, %f978;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs121, %f977;}
+
+	// inline asm
+	mov.u16 	%rs128, 0;
+	st.v4.u16 	[%rd213], {%rs121, %rs122, %rs123, %rs128};
+	bra.uni 	BB0_146;
+
+BB0_145:
+	mov.u64 	%rd226, image_RNM0;
+	cvta.global.u64 	%rd221, %rd226;
+	mov.u32 	%r359, 8;
+	// inline asm
+	call (%rd220), _rt_buffer_get_64, (%rd221, %r105, %r359, %rd23, %rd24, %rd30, %rd30);
+	// inline asm
+	mov.f32 	%f980, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs129, %f980;}
+
+	// inline asm
+	mov.u16 	%rs130, 0;
+	st.v4.u16 	[%rd220], {%rs129, %rs129, %rs129, %rs130};
+
+BB0_146:
+	ld.global.u32 	%r360, [additive];
+	setp.eq.s32	%p146, %r360, 0;
+	@%p146 bra 	BB0_148;
+
+	mov.u64 	%rd239, image_RNM1;
+	cvta.global.u64 	%rd228, %rd239;
+	mov.u32 	%r364, 8;
+	// inline asm
+	call (%rd227), _rt_buffer_get_64, (%rd228, %r105, %r364, %rd23, %rd24, %rd30, %rd30);
+	// inline asm
+	ld.v4.u16 	{%rs137, %rs138, %rs139, %rs140}, [%rd227];
+	// inline asm
+	{  cvt.f32.f16 %f981, %rs137;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f982, %rs138;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f983, %rs139;}
+
+	// inline asm
+	// inline asm
+	call (%rd233), _rt_buffer_get_64, (%rd228, %r105, %r364, %rd23, %rd24, %rd30, %rd30);
+	// inline asm
+	add.f32 	%f984, %f981, 0f00000000;
+	add.f32 	%f985, %f982, 0f00000000;
+	add.f32 	%f986, %f983, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs136, %f986;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs135, %f985;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs134, %f984;}
+
+	// inline asm
+	mov.u16 	%rs141, 0;
+	st.v4.u16 	[%rd233], {%rs134, %rs135, %rs136, %rs141};
+	bra.uni 	BB0_149;
+
+BB0_148:
+	mov.u64 	%rd246, image_RNM1;
+	cvta.global.u64 	%rd241, %rd246;
+	mov.u32 	%r366, 8;
+	// inline asm
+	call (%rd240), _rt_buffer_get_64, (%rd241, %r105, %r366, %rd23, %rd24, %rd30, %rd30);
+	// inline asm
+	mov.f32 	%f987, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs142, %f987;}
+
+	// inline asm
+	mov.u16 	%rs143, 0;
+	st.v4.u16 	[%rd240], {%rs142, %rs142, %rs142, %rs143};
+
+BB0_149:
+	ld.global.u32 	%r367, [additive];
+	setp.eq.s32	%p147, %r367, 0;
+	@%p147 bra 	BB0_151;
+
+	mov.u64 	%rd259, image_RNM2;
+	cvta.global.u64 	%rd248, %rd259;
+	mov.u32 	%r371, 8;
+	// inline asm
+	call (%rd247), _rt_buffer_get_64, (%rd248, %r105, %r371, %rd23, %rd24, %rd30, %rd30);
+	// inline asm
+	ld.v4.u16 	{%rs150, %rs151, %rs152, %rs153}, [%rd247];
+	// inline asm
+	{  cvt.f32.f16 %f988, %rs150;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f989, %rs151;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f990, %rs152;}
+
+	// inline asm
+	// inline asm
+	call (%rd253), _rt_buffer_get_64, (%rd248, %r105, %r371, %rd23, %rd24, %rd30, %rd30);
+	// inline asm
+	add.f32 	%f991, %f988, 0f00000000;
+	add.f32 	%f992, %f989, 0f00000000;
+	add.f32 	%f993, %f990, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs149, %f993;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs148, %f992;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs147, %f991;}
+
+	// inline asm
+	mov.u16 	%rs154, 0;
+	st.v4.u16 	[%rd253], {%rs147, %rs148, %rs149, %rs154};
+	bra.uni 	BB0_152;
+
+BB0_151:
+	mov.u64 	%rd266, image_RNM2;
+	cvta.global.u64 	%rd261, %rd266;
+	mov.u32 	%r373, 8;
+	// inline asm
+	call (%rd260), _rt_buffer_get_64, (%rd261, %r105, %r373, %rd23, %rd24, %rd30, %rd30);
+	// inline asm
+	mov.f32 	%f994, 0f00000000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs155, %f994;}
+
+	// inline asm
+	mov.u16 	%rs156, 0;
+	st.v4.u16 	[%rd260], {%rs155, %rs155, %rs155, %rs156};
+	bra.uni 	BB0_152;
+
+BB0_72:
+	setp.geu.f32	%p71, %f1082, 0f00000000;
+	@%p71 bra 	BB0_75;
+
+	mov.f32 	%f1044, 0f3EE8BA2E;
+	cvt.rzi.f32.f32	%f516, %f1044;
+	setp.neu.f32	%p72, %f516, 0f3EE8BA2E;
+	selp.f32	%f1088, 0f7FFFFFFF, %f1088, %p72;
+
+BB0_75:
+	abs.f32 	%f1041, %f1082;
+	add.f32 	%f518, %f1041, 0f3EE8BA2E;
+	mov.b32 	 %r256, %f518;
+	setp.lt.s32	%p74, %r256, 2139095040;
+	@%p74 bra 	BB0_80;
+
+	abs.f32 	%f1042, %f1082;
+	setp.gtu.f32	%p75, %f1042, 0f7F800000;
+	@%p75 bra 	BB0_79;
+	bra.uni 	BB0_77;
+
+BB0_79:
+	add.f32 	%f1088, %f1082, 0f3EE8BA2E;
+	bra.uni 	BB0_80;
+
+BB0_77:
+	abs.f32 	%f1043, %f1082;
+	setp.neu.f32	%p76, %f1043, 0f7F800000;
+	@%p76 bra 	BB0_80;
+
+	selp.f32	%f1088, 0fFF800000, 0f7F800000, %p2;
+
+BB0_80:
+	mul.f32 	%f519, %f1088, 0f437F0000;
+	setp.eq.f32	%p77, %f1082, 0f3F800000;
+	selp.f32	%f520, 0f437F0000, %f519, %p77;
+	cvt.rzi.u32.f32	%r257, %f520;
+	cvt.u16.u32	%rs13, %r257;
+	mov.u16 	%rs14, 255;
+	st.v2.u8 	[%rd58], {%rs13, %rs14};
+	ld.global.u32 	%r407, [imageEnabled];
+
+BB0_81:
+	and.b32  	%r258, %r407, 1;
+	setp.eq.b32	%p78, %r258, 1;
+	@!%p78 bra 	BB0_116;
+	bra.uni 	BB0_82;
+
+BB0_82:
+	mov.f32 	%f1016, 0fB5BFBE8E;
+	mov.f32 	%f1015, 0fBF317200;
+	mov.f32 	%f1014, 0f00000000;
+	mov.f32 	%f1013, 0f35BFBE8E;
+	mov.f32 	%f1012, 0f3F317200;
+	mov.f32 	%f1011, 0f3DAAAABD;
+	mov.f32 	%f1010, 0f3C4CAF63;
+	mov.f32 	%f1009, 0f3B18F0FE;
+	abs.f32 	%f107, %f73;
+	setp.lt.f32	%p79, %f107, 0f00800000;
+	mul.f32 	%f526, %f107, 0f4B800000;
+	selp.f32	%f527, 0fC3170000, 0fC2FE0000, %p79;
+	selp.f32	%f528, %f526, %f107, %p79;
+	mov.b32 	 %r259, %f528;
+	and.b32  	%r260, %r259, 8388607;
+	or.b32  	%r261, %r260, 1065353216;
+	mov.b32 	 %f529, %r261;
+	shr.u32 	%r262, %r259, 23;
+	cvt.rn.f32.u32	%f530, %r262;
+	add.f32 	%f531, %f527, %f530;
+	setp.gt.f32	%p80, %f529, 0f3FB504F3;
+	mul.f32 	%f532, %f529, 0f3F000000;
+	add.f32 	%f533, %f531, 0f3F800000;
+	selp.f32	%f534, %f532, %f529, %p80;
+	selp.f32	%f535, %f533, %f531, %p80;
+	add.f32 	%f536, %f534, 0fBF800000;
+	add.f32 	%f522, %f534, 0f3F800000;
+	// inline asm
+	rcp.approx.ftz.f32 %f521,%f522;
+	// inline asm
+	add.f32 	%f537, %f536, %f536;
+	mul.f32 	%f538, %f521, %f537;
+	mul.f32 	%f539, %f538, %f538;
+	fma.rn.f32 	%f542, %f1009, %f539, %f1010;
+	fma.rn.f32 	%f544, %f542, %f539, %f1011;
+	mul.rn.f32 	%f545, %f544, %f539;
+	mul.rn.f32 	%f546, %f545, %f538;
+	sub.f32 	%f547, %f536, %f538;
+	neg.f32 	%f548, %f538;
+	add.f32 	%f549, %f547, %f547;
+	fma.rn.f32 	%f550, %f548, %f536, %f549;
+	mul.rn.f32 	%f551, %f521, %f550;
+	add.f32 	%f552, %f546, %f538;
+	sub.f32 	%f553, %f538, %f552;
+	add.f32 	%f554, %f546, %f553;
+	add.f32 	%f555, %f551, %f554;
+	add.f32 	%f556, %f552, %f555;
+	sub.f32 	%f557, %f552, %f556;
+	add.f32 	%f558, %f555, %f557;
+	mul.rn.f32 	%f560, %f535, %f1012;
+	mul.rn.f32 	%f562, %f535, %f1013;
+	add.f32 	%f563, %f560, %f556;
+	sub.f32 	%f564, %f560, %f563;
+	add.f32 	%f565, %f556, %f564;
+	add.f32 	%f566, %f558, %f565;
+	add.f32 	%f567, %f562, %f566;
+	add.f32 	%f568, %f563, %f567;
+	sub.f32 	%f569, %f563, %f568;
+	add.f32 	%f570, %f567, %f569;
+	mov.f32 	%f571, 0f3EE66666;
+	mul.rn.f32 	%f572, %f571, %f568;
+	neg.f32 	%f573, %f572;
+	fma.rn.f32 	%f574, %f571, %f568, %f573;
+	fma.rn.f32 	%f575, %f571, %f570, %f574;
+	fma.rn.f32 	%f577, %f1014, %f568, %f575;
+	add.rn.f32 	%f578, %f572, %f577;
+	neg.f32 	%f579, %f578;
+	add.rn.f32 	%f580, %f572, %f579;
+	add.rn.f32 	%f581, %f580, %f577;
+	mov.b32 	 %r263, %f578;
+	setp.eq.s32	%p81, %r263, 1118925336;
+	add.s32 	%r264, %r263, -1;
+	mov.b32 	 %f582, %r264;
+	add.f32 	%f583, %f581, 0f37000000;
+	selp.f32	%f584, %f582, %f578, %p81;
+	selp.f32	%f108, %f583, %f581, %p81;
+	mul.f32 	%f585, %f584, 0f3FB8AA3B;
+	cvt.rzi.f32.f32	%f586, %f585;
+	fma.rn.f32 	%f588, %f586, %f1015, %f584;
+	fma.rn.f32 	%f590, %f586, %f1016, %f588;
+	mul.f32 	%f591, %f590, 0f3FB8AA3B;
+	ex2.approx.ftz.f32 	%f592, %f591;
+	add.f32 	%f593, %f586, 0f00000000;
+	ex2.approx.f32 	%f594, %f593;
+	mul.f32 	%f595, %f592, %f594;
+	setp.lt.f32	%p82, %f584, 0fC2D20000;
+	selp.f32	%f596, 0f00000000, %f595, %p82;
+	setp.gt.f32	%p83, %f584, 0f42D20000;
+	selp.f32	%f1089, 0f7F800000, %f596, %p83;
+	setp.eq.f32	%p84, %f1089, 0f7F800000;
+	@%p84 bra 	BB0_84;
+
+	fma.rn.f32 	%f1089, %f1089, %f108, %f1089;
+
+BB0_84:
+	mov.f32 	%f1048, 0f3E666666;
+	cvt.rzi.f32.f32	%f1047, %f1048;
+	fma.rn.f32 	%f1046, %f1047, 0fC0000000, 0f3EE66666;
+	abs.f32 	%f1045, %f1046;
+	setp.lt.f32	%p85, %f73, 0f00000000;
+	setp.eq.f32	%p86, %f1045, 0f3F800000;
+	and.pred  	%p3, %p85, %p86;
+	mov.b32 	 %r265, %f1089;
+	xor.b32  	%r266, %r265, -2147483648;
+	mov.b32 	 %f597, %r266;
+	selp.f32	%f1091, %f597, %f1089, %p3;
+	setp.eq.f32	%p87, %f73, 0f00000000;
+	@%p87 bra 	BB0_87;
+	bra.uni 	BB0_85;
+
+BB0_87:
+	add.f32 	%f600, %f73, %f73;
+	selp.f32	%f1091, %f600, 0f00000000, %p86;
+	bra.uni 	BB0_88;
+
+BB0_85:
+	setp.geu.f32	%p88, %f73, 0f00000000;
+	@%p88 bra 	BB0_88;
+
+	mov.f32 	%f1056, 0f3EE66666;
+	cvt.rzi.f32.f32	%f599, %f1056;
+	setp.neu.f32	%p89, %f599, 0f3EE66666;
+	selp.f32	%f1091, 0f7FFFFFFF, %f1091, %p89;
+
+BB0_88:
+	abs.f32 	%f1049, %f73;
+	add.f32 	%f601, %f1049, 0f3EE66666;
+	mov.b32 	 %r267, %f601;
+	setp.lt.s32	%p91, %r267, 2139095040;
+	@%p91 bra 	BB0_93;
+
+	abs.f32 	%f1054, %f73;
+	setp.gtu.f32	%p92, %f1054, 0f7F800000;
+	@%p92 bra 	BB0_92;
+	bra.uni 	BB0_90;
+
+BB0_92:
+	add.f32 	%f1091, %f73, 0f3EE66666;
+	bra.uni 	BB0_93;
+
+BB0_90:
+	abs.f32 	%f1055, %f73;
+	setp.neu.f32	%p93, %f1055, 0f7F800000;
+	@%p93 bra 	BB0_93;
+
+	selp.f32	%f1091, 0fFF800000, 0f7F800000, %p3;
+
+BB0_93:
+	mov.f32 	%f1050, 0f3EE66666;
+	mov.f32 	%f1024, 0fB5BFBE8E;
+	mov.f32 	%f1023, 0fBF317200;
+	mov.f32 	%f1022, 0f00000000;
+	mov.f32 	%f1021, 0f35BFBE8E;
+	mov.f32 	%f1020, 0f3F317200;
+	mov.f32 	%f1019, 0f3DAAAABD;
+	mov.f32 	%f1018, 0f3C4CAF63;
+	mov.f32 	%f1017, 0f3B18F0FE;
+	setp.eq.f32	%p94, %f73, 0f3F800000;
+	selp.f32	%f119, 0f3F800000, %f1091, %p94;
+	abs.f32 	%f120, %f74;
+	setp.lt.f32	%p95, %f120, 0f00800000;
+	mul.f32 	%f604, %f120, 0f4B800000;
+	selp.f32	%f605, 0fC3170000, 0fC2FE0000, %p95;
+	selp.f32	%f606, %f604, %f120, %p95;
+	mov.b32 	 %r268, %f606;
+	and.b32  	%r269, %r268, 8388607;
+	or.b32  	%r270, %r269, 1065353216;
+	mov.b32 	 %f607, %r270;
+	shr.u32 	%r271, %r268, 23;
+	cvt.rn.f32.u32	%f608, %r271;
+	add.f32 	%f609, %f605, %f608;
+	setp.gt.f32	%p96, %f607, 0f3FB504F3;
+	mul.f32 	%f610, %f607, 0f3F000000;
+	add.f32 	%f611, %f609, 0f3F800000;
+	selp.f32	%f612, %f610, %f607, %p96;
+	selp.f32	%f613, %f611, %f609, %p96;
+	add.f32 	%f614, %f612, 0fBF800000;
+	add.f32 	%f603, %f612, 0f3F800000;
+	// inline asm
+	rcp.approx.ftz.f32 %f602,%f603;
+	// inline asm
+	add.f32 	%f615, %f614, %f614;
+	mul.f32 	%f616, %f602, %f615;
+	mul.f32 	%f617, %f616, %f616;
+	fma.rn.f32 	%f620, %f1017, %f617, %f1018;
+	fma.rn.f32 	%f622, %f620, %f617, %f1019;
+	mul.rn.f32 	%f623, %f622, %f617;
+	mul.rn.f32 	%f624, %f623, %f616;
+	sub.f32 	%f625, %f614, %f616;
+	neg.f32 	%f626, %f616;
+	add.f32 	%f627, %f625, %f625;
+	fma.rn.f32 	%f628, %f626, %f614, %f627;
+	mul.rn.f32 	%f629, %f602, %f628;
+	add.f32 	%f630, %f624, %f616;
+	sub.f32 	%f631, %f616, %f630;
+	add.f32 	%f632, %f624, %f631;
+	add.f32 	%f633, %f629, %f632;
+	add.f32 	%f634, %f630, %f633;
+	sub.f32 	%f635, %f630, %f634;
+	add.f32 	%f636, %f633, %f635;
+	mul.rn.f32 	%f638, %f613, %f1020;
+	mul.rn.f32 	%f640, %f613, %f1021;
+	add.f32 	%f641, %f638, %f634;
+	sub.f32 	%f642, %f638, %f641;
+	add.f32 	%f643, %f634, %f642;
+	add.f32 	%f644, %f636, %f643;
+	add.f32 	%f645, %f640, %f644;
+	add.f32 	%f646, %f641, %f645;
+	sub.f32 	%f647, %f641, %f646;
+	add.f32 	%f648, %f645, %f647;
+	mul.rn.f32 	%f650, %f1050, %f646;
+	neg.f32 	%f651, %f650;
+	fma.rn.f32 	%f652, %f1050, %f646, %f651;
+	fma.rn.f32 	%f653, %f1050, %f648, %f652;
+	fma.rn.f32 	%f655, %f1022, %f646, %f653;
+	add.rn.f32 	%f656, %f650, %f655;
+	neg.f32 	%f657, %f656;
+	add.rn.f32 	%f658, %f650, %f657;
+	add.rn.f32 	%f659, %f658, %f655;
+	mov.b32 	 %r272, %f656;
+	setp.eq.s32	%p97, %r272, 1118925336;
+	add.s32 	%r273, %r272, -1;
+	mov.b32 	 %f660, %r273;
+	add.f32 	%f661, %f659, 0f37000000;
+	selp.f32	%f662, %f660, %f656, %p97;
+	selp.f32	%f121, %f661, %f659, %p97;
+	mul.f32 	%f663, %f662, 0f3FB8AA3B;
+	cvt.rzi.f32.f32	%f664, %f663;
+	fma.rn.f32 	%f666, %f664, %f1023, %f662;
+	fma.rn.f32 	%f668, %f664, %f1024, %f666;
+	mul.f32 	%f669, %f668, 0f3FB8AA3B;
+	ex2.approx.ftz.f32 	%f670, %f669;
+	add.f32 	%f671, %f664, 0f00000000;
+	ex2.approx.f32 	%f672, %f671;
+	mul.f32 	%f673, %f670, %f672;
+	setp.lt.f32	%p98, %f662, 0fC2D20000;
+	selp.f32	%f674, 0f00000000, %f673, %p98;
+	setp.gt.f32	%p99, %f662, 0f42D20000;
+	selp.f32	%f1092, 0f7F800000, %f674, %p99;
+	setp.eq.f32	%p100, %f1092, 0f7F800000;
+	@%p100 bra 	BB0_95;
+
+	fma.rn.f32 	%f1092, %f1092, %f121, %f1092;
+
+BB0_95:
+	setp.lt.f32	%p101, %f74, 0f00000000;
+	and.pred  	%p4, %p101, %p86;
+	mov.b32 	 %r274, %f1092;
+	xor.b32  	%r275, %r274, -2147483648;
+	mov.b32 	 %f675, %r275;
+	selp.f32	%f1094, %f675, %f1092, %p4;
+	setp.eq.f32	%p103, %f74, 0f00000000;
+	@%p103 bra 	BB0_98;
+	bra.uni 	BB0_96;
+
+BB0_98:
+	add.f32 	%f678, %f74, %f74;
+	selp.f32	%f1094, %f678, 0f00000000, %p86;
+	bra.uni 	BB0_99;
+
+BB0_96:
+	setp.geu.f32	%p104, %f74, 0f00000000;
+	@%p104 bra 	BB0_99;
+
+	mov.f32 	%f1053, 0f3EE66666;
+	cvt.rzi.f32.f32	%f677, %f1053;
+	setp.neu.f32	%p105, %f677, 0f3EE66666;
+	selp.f32	%f1094, 0f7FFFFFFF, %f1094, %p105;
+
+BB0_99:
+	abs.f32 	%f1057, %f74;
+	add.f32 	%f679, %f1057, 0f3EE66666;
+	mov.b32 	 %r276, %f679;
+	setp.lt.s32	%p107, %r276, 2139095040;
+	@%p107 bra 	BB0_104;
+
+	abs.f32 	%f1058, %f74;
+	setp.gtu.f32	%p108, %f1058, 0f7F800000;
+	@%p108 bra 	BB0_103;
+	bra.uni 	BB0_101;
+
+BB0_103:
+	add.f32 	%f1094, %f74, 0f3EE66666;
+	bra.uni 	BB0_104;
+
+BB0_101:
+	abs.f32 	%f1059, %f74;
+	setp.neu.f32	%p109, %f1059, 0f7F800000;
+	@%p109 bra 	BB0_104;
+
+	selp.f32	%f1094, 0fFF800000, 0f7F800000, %p4;
+
+BB0_104:
+	mov.f32 	%f1051, 0f3EE66666;
+	mov.f32 	%f1032, 0fB5BFBE8E;
+	mov.f32 	%f1031, 0fBF317200;
+	mov.f32 	%f1030, 0f00000000;
+	mov.f32 	%f1029, 0f35BFBE8E;
+	mov.f32 	%f1028, 0f3F317200;
+	mov.f32 	%f1027, 0f3DAAAABD;
+	mov.f32 	%f1026, 0f3C4CAF63;
+	mov.f32 	%f1025, 0f3B18F0FE;
+	setp.eq.f32	%p110, %f74, 0f3F800000;
+	selp.f32	%f132, 0f3F800000, %f1094, %p110;
+	abs.f32 	%f133, %f75;
+	setp.lt.f32	%p111, %f133, 0f00800000;
+	mul.f32 	%f682, %f133, 0f4B800000;
+	selp.f32	%f683, 0fC3170000, 0fC2FE0000, %p111;
+	selp.f32	%f684, %f682, %f133, %p111;
+	mov.b32 	 %r277, %f684;
+	and.b32  	%r278, %r277, 8388607;
+	or.b32  	%r279, %r278, 1065353216;
+	mov.b32 	 %f685, %r279;
+	shr.u32 	%r280, %r277, 23;
+	cvt.rn.f32.u32	%f686, %r280;
+	add.f32 	%f687, %f683, %f686;
+	setp.gt.f32	%p112, %f685, 0f3FB504F3;
+	mul.f32 	%f688, %f685, 0f3F000000;
+	add.f32 	%f689, %f687, 0f3F800000;
+	selp.f32	%f690, %f688, %f685, %p112;
+	selp.f32	%f691, %f689, %f687, %p112;
+	add.f32 	%f692, %f690, 0fBF800000;
+	add.f32 	%f681, %f690, 0f3F800000;
+	// inline asm
+	rcp.approx.ftz.f32 %f680,%f681;
+	// inline asm
+	add.f32 	%f693, %f692, %f692;
+	mul.f32 	%f694, %f680, %f693;
+	mul.f32 	%f695, %f694, %f694;
+	fma.rn.f32 	%f698, %f1025, %f695, %f1026;
+	fma.rn.f32 	%f700, %f698, %f695, %f1027;
+	mul.rn.f32 	%f701, %f700, %f695;
+	mul.rn.f32 	%f702, %f701, %f694;
+	sub.f32 	%f703, %f692, %f694;
+	neg.f32 	%f704, %f694;
+	add.f32 	%f705, %f703, %f703;
+	fma.rn.f32 	%f706, %f704, %f692, %f705;
+	mul.rn.f32 	%f707, %f680, %f706;
+	add.f32 	%f708, %f702, %f694;
+	sub.f32 	%f709, %f694, %f708;
+	add.f32 	%f710, %f702, %f709;
+	add.f32 	%f711, %f707, %f710;
+	add.f32 	%f712, %f708, %f711;
+	sub.f32 	%f713, %f708, %f712;
+	add.f32 	%f714, %f711, %f713;
+	mul.rn.f32 	%f716, %f691, %f1028;
+	mul.rn.f32 	%f718, %f691, %f1029;
+	add.f32 	%f719, %f716, %f712;
+	sub.f32 	%f720, %f716, %f719;
+	add.f32 	%f721, %f712, %f720;
+	add.f32 	%f722, %f714, %f721;
+	add.f32 	%f723, %f718, %f722;
+	add.f32 	%f724, %f719, %f723;
+	sub.f32 	%f725, %f719, %f724;
+	add.f32 	%f726, %f723, %f725;
+	mul.rn.f32 	%f728, %f1051, %f724;
+	neg.f32 	%f729, %f728;
+	fma.rn.f32 	%f730, %f1051, %f724, %f729;
+	fma.rn.f32 	%f731, %f1051, %f726, %f730;
+	fma.rn.f32 	%f733, %f1030, %f724, %f731;
+	add.rn.f32 	%f734, %f728, %f733;
+	neg.f32 	%f735, %f734;
+	add.rn.f32 	%f736, %f728, %f735;
+	add.rn.f32 	%f737, %f736, %f733;
+	mov.b32 	 %r281, %f734;
+	setp.eq.s32	%p113, %r281, 1118925336;
+	add.s32 	%r282, %r281, -1;
+	mov.b32 	 %f738, %r282;
+	add.f32 	%f739, %f737, 0f37000000;
+	selp.f32	%f740, %f738, %f734, %p113;
+	selp.f32	%f134, %f739, %f737, %p113;
+	mul.f32 	%f741, %f740, 0f3FB8AA3B;
+	cvt.rzi.f32.f32	%f742, %f741;
+	fma.rn.f32 	%f744, %f742, %f1031, %f740;
+	fma.rn.f32 	%f746, %f742, %f1032, %f744;
+	mul.f32 	%f747, %f746, 0f3FB8AA3B;
+	ex2.approx.ftz.f32 	%f748, %f747;
+	add.f32 	%f749, %f742, 0f00000000;
+	ex2.approx.f32 	%f750, %f749;
+	mul.f32 	%f751, %f748, %f750;
+	setp.lt.f32	%p114, %f740, 0fC2D20000;
+	selp.f32	%f752, 0f00000000, %f751, %p114;
+	setp.gt.f32	%p115, %f740, 0f42D20000;
+	selp.f32	%f1095, 0f7F800000, %f752, %p115;
+	setp.eq.f32	%p116, %f1095, 0f7F800000;
+	@%p116 bra 	BB0_106;
+
+	fma.rn.f32 	%f1095, %f1095, %f134, %f1095;
+
+BB0_106:
+	setp.lt.f32	%p117, %f75, 0f00000000;
+	and.pred  	%p5, %p117, %p86;
+	mov.b32 	 %r283, %f1095;
+	xor.b32  	%r284, %r283, -2147483648;
+	mov.b32 	 %f753, %r284;
+	selp.f32	%f1097, %f753, %f1095, %p5;
+	setp.eq.f32	%p119, %f75, 0f00000000;
+	@%p119 bra 	BB0_109;
+	bra.uni 	BB0_107;
+
+BB0_109:
+	add.f32 	%f756, %f75, %f75;
+	selp.f32	%f1097, %f756, 0f00000000, %p86;
+	bra.uni 	BB0_110;
+
+BB0_107:
+	setp.geu.f32	%p120, %f75, 0f00000000;
+	@%p120 bra 	BB0_110;
+
+	mov.f32 	%f1052, 0f3EE66666;
+	cvt.rzi.f32.f32	%f755, %f1052;
+	setp.neu.f32	%p121, %f755, 0f3EE66666;
+	selp.f32	%f1097, 0f7FFFFFFF, %f1097, %p121;
+
+BB0_110:
+	abs.f32 	%f1060, %f75;
+	add.f32 	%f757, %f1060, 0f3EE66666;
+	mov.b32 	 %r285, %f757;
+	setp.lt.s32	%p123, %r285, 2139095040;
+	@%p123 bra 	BB0_115;
+
+	abs.f32 	%f1061, %f75;
+	setp.gtu.f32	%p124, %f1061, 0f7F800000;
+	@%p124 bra 	BB0_114;
+	bra.uni 	BB0_112;
+
+BB0_114:
+	add.f32 	%f1097, %f75, 0f3EE66666;
+	bra.uni 	BB0_115;
+
+BB0_112:
+	abs.f32 	%f1062, %f75;
+	setp.neu.f32	%p125, %f1062, 0f7F800000;
+	@%p125 bra 	BB0_115;
+
+	selp.f32	%f1097, 0fFF800000, 0f7F800000, %p5;
+
+BB0_115:
+	mov.u32 	%r374, 4;
+	setp.eq.f32	%p126, %f75, 0f3F800000;
+	selp.f32	%f758, 0f3F800000, %f1097, %p126;
+	cvt.u64.u32	%rd68, %r3;
+	cvt.u64.u32	%rd67, %r2;
+	mov.u64 	%rd71, image;
+	cvta.global.u64 	%rd66, %rd71;
+	// inline asm
+	call (%rd65), _rt_buffer_get_64, (%rd66, %r105, %r374, %rd67, %rd68, %rd30, %rd30);
+	// inline asm
+	cvt.sat.f32.f32	%f759, %f758;
+	mul.f32 	%f760, %f759, 0f437FFD71;
+	cvt.rzi.u32.f32	%r288, %f760;
+	cvt.sat.f32.f32	%f761, %f132;
+	mul.f32 	%f762, %f761, 0f437FFD71;
+	cvt.rzi.u32.f32	%r289, %f762;
+	cvt.sat.f32.f32	%f763, %f119;
+	mul.f32 	%f764, %f763, 0f437FFD71;
+	cvt.rzi.u32.f32	%r290, %f764;
+	cvt.u16.u32	%rs15, %r288;
+	cvt.u16.u32	%rs16, %r290;
+	cvt.u16.u32	%rs17, %r289;
+	mov.u16 	%rs18, 255;
+	st.v4.u8 	[%rd65], {%rs15, %rs17, %rs16, %rs18};
+	ld.global.u32 	%r407, [imageEnabled];
+
+BB0_116:
+	and.b32  	%r291, %r407, 4;
+	setp.eq.s32	%p127, %r291, 0;
+	@%p127 bra 	BB0_120;
+
+	ld.global.u32 	%r292, [additive];
+	setp.eq.s32	%p128, %r292, 0;
+	cvt.u64.u32	%rd16, %r2;
+	cvt.u64.u32	%rd17, %r3;
+	mov.f32 	%f765, 0f3F800000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs19, %f765;}
+
+	// inline asm
+	@%p128 bra 	BB0_119;
+
+	mov.u64 	%rd84, image_HDR;
+	cvta.global.u64 	%rd73, %rd84;
+	mov.u32 	%r296, 8;
+	// inline asm
+	call (%rd72), _rt_buffer_get_64, (%rd73, %r105, %r296, %rd16, %rd17, %rd30, %rd30);
+	// inline asm
+	ld.v4.u16 	{%rs26, %rs27, %rs28, %rs29}, [%rd72];
+	// inline asm
+	{  cvt.f32.f16 %f766, %rs26;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f767, %rs27;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f768, %rs28;}
+
+	// inline asm
+	// inline asm
+	call (%rd78), _rt_buffer_get_64, (%rd73, %r105, %r296, %rd16, %rd17, %rd30, %rd30);
+	// inline asm
+	add.f32 	%f769, %f73, %f766;
+	add.f32 	%f770, %f74, %f767;
+	add.f32 	%f771, %f75, %f768;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs25, %f771;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs24, %f770;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs23, %f769;}
+
+	// inline asm
+	st.v4.u16 	[%rd78], {%rs23, %rs24, %rs25, %rs19};
+	bra.uni 	BB0_120;
+
+BB0_119:
+	mov.u64 	%rd91, image_HDR;
+	cvta.global.u64 	%rd86, %rd91;
+	mov.u32 	%r298, 8;
+	// inline asm
+	call (%rd85), _rt_buffer_get_64, (%rd86, %r105, %r298, %rd16, %rd17, %rd30, %rd30);
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs32, %f75;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs31, %f74;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs30, %f73;}
+
+	// inline asm
+	st.v4.u16 	[%rd85], {%rs30, %rs31, %rs32, %rs19};
+
+BB0_120:
+	mov.f32 	%f1098, 0f00000000;
+	mov.u32 	%r375, 4;
+	ld.global.v2.u32 	{%r301, %r302}, [pixelID];
+	cvt.u64.u32	%rd94, %r301;
+	cvt.u64.u32	%rd95, %r302;
+	mov.u64 	%rd98, uvtangent;
+	cvta.global.u64 	%rd93, %rd98;
+	// inline asm
+	call (%rd92), _rt_buffer_get_64, (%rd93, %r105, %r375, %rd94, %rd95, %rd30, %rd30);
+	// inline asm
+	ld.u32 	%r94, [%rd92];
+	shr.u32 	%r95, %r94, 16;
+	cvt.u16.u32	%rs33, %r95;
+	and.b16  	%rs34, %rs33, 255;
+	cvt.u16.u32	%rs35, %r94;
+	or.b16  	%rs36, %rs35, %rs34;
+	setp.eq.s16	%p129, %rs36, 0;
+	mov.f32 	%f1099, %f1098;
+	mov.f32 	%f1100, %f1098;
+	@%p129 bra 	BB0_122;
+
+	ld.u8 	%rs37, [%rd92+1];
+	and.b16  	%rs39, %rs35, 255;
+	cvt.rn.f32.u16	%f778, %rs39;
+	div.rn.f32 	%f779, %f778, 0f437F0000;
+	fma.rn.f32 	%f780, %f779, 0f40000000, 0fBF800000;
+	cvt.rn.f32.u16	%f781, %rs37;
+	div.rn.f32 	%f782, %f781, 0f437F0000;
+	fma.rn.f32 	%f783, %f782, 0f40000000, 0fBF800000;
+	cvt.rn.f32.u16	%f784, %rs34;
+	div.rn.f32 	%f785, %f784, 0f437F0000;
+	fma.rn.f32 	%f786, %f785, 0f40000000, 0fBF800000;
+	mul.f32 	%f787, %f783, %f783;
+	fma.rn.f32 	%f788, %f780, %f780, %f787;
+	fma.rn.f32 	%f789, %f786, %f786, %f788;
+	sqrt.rn.f32 	%f790, %f789;
+	rcp.rn.f32 	%f791, %f790;
+	mul.f32 	%f1098, %f780, %f791;
+	mul.f32 	%f1099, %f783, %f791;
+	mul.f32 	%f1100, %f786, %f791;
+
+BB0_122:
+	mov.f32 	%f1101, 0f00000000;
+	mov.u32 	%r376, 4;
+	mul.f32 	%f795, %f1065, %f1099;
+	mul.f32 	%f796, %f1064, %f1100;
+	sub.f32 	%f797, %f796, %f795;
+	mul.f32 	%f798, %f1063, %f1100;
+	mul.f32 	%f799, %f1065, %f1098;
+	sub.f32 	%f800, %f799, %f798;
+	mul.f32 	%f801, %f1064, %f1098;
+	mul.f32 	%f802, %f1063, %f1099;
+	sub.f32 	%f803, %f802, %f801;
+	setp.lt.u32	%p130, %r94, 16777216;
+	selp.f32	%f804, 0fBF800000, 0f3F800000, %p130;
+	mul.f32 	%f805, %f797, %f804;
+	mul.f32 	%f806, %f800, %f804;
+	mul.f32 	%f807, %f803, %f804;
+	mul.f32 	%f808, %f805, 0f00000000;
+	mul.f32 	%f809, %f806, 0f00000000;
+	mul.f32 	%f810, %f807, 0f00000000;
+	fma.rn.f32 	%f811, %f1098, 0f3F5105EC, %f808;
+	fma.rn.f32 	%f812, %f1099, 0f3F5105EC, %f809;
+	fma.rn.f32 	%f813, %f1100, 0f3F5105EC, %f810;
+	mul.f32 	%f151, %f1063, 0f3F13CD3A;
+	add.f32 	%f152, %f151, %f811;
+	mul.f32 	%f153, %f1064, 0f3F13CD3A;
+	add.f32 	%f154, %f153, %f812;
+	mul.f32 	%f155, %f1065, 0f3F13CD3A;
+	add.f32 	%f156, %f155, %f813;
+	ld.global.v2.u32 	{%r307, %r308}, [pixelID];
+	cvt.u64.u32	%rd101, %r307;
+	cvt.u64.u32	%rd102, %r308;
+	// inline asm
+	call (%rd99), _rt_buffer_get_64, (%rd93, %r105, %r376, %rd101, %rd102, %rd30, %rd30);
+	// inline asm
+	ld.u32 	%r96, [%rd99];
+	shr.u32 	%r97, %r96, 16;
+	cvt.u16.u32	%rs42, %r97;
+	and.b16  	%rs43, %rs42, 255;
+	cvt.u16.u32	%rs44, %r96;
+	or.b16  	%rs45, %rs44, %rs43;
+	setp.eq.s16	%p131, %rs45, 0;
+	mov.f32 	%f1102, %f1101;
+	mov.f32 	%f1103, %f1101;
+	@%p131 bra 	BB0_124;
+
+	ld.u8 	%rs46, [%rd99+1];
+	and.b16  	%rs48, %rs44, 255;
+	cvt.rn.f32.u16	%f814, %rs48;
+	div.rn.f32 	%f815, %f814, 0f437F0000;
+	fma.rn.f32 	%f816, %f815, 0f40000000, 0fBF800000;
+	cvt.rn.f32.u16	%f817, %rs46;
+	div.rn.f32 	%f818, %f817, 0f437F0000;
+	fma.rn.f32 	%f819, %f818, 0f40000000, 0fBF800000;
+	cvt.rn.f32.u16	%f820, %rs43;
+	div.rn.f32 	%f821, %f820, 0f437F0000;
+	fma.rn.f32 	%f822, %f821, 0f40000000, 0fBF800000;
+	mul.f32 	%f823, %f819, %f819;
+	fma.rn.f32 	%f824, %f816, %f816, %f823;
+	fma.rn.f32 	%f825, %f822, %f822, %f824;
+	sqrt.rn.f32 	%f826, %f825;
+	rcp.rn.f32 	%f827, %f826;
+	mul.f32 	%f1101, %f816, %f827;
+	mul.f32 	%f1102, %f819, %f827;
+	mul.f32 	%f1103, %f822, %f827;
+
+BB0_124:
+	mov.f32 	%f1104, 0f00000000;
+	mov.u32 	%r377, 4;
+	mul.f32 	%f831, %f1065, %f1102;
+	mul.f32 	%f832, %f1064, %f1103;
+	sub.f32 	%f833, %f832, %f831;
+	mul.f32 	%f834, %f1063, %f1103;
+	mul.f32 	%f835, %f1065, %f1101;
+	sub.f32 	%f836, %f835, %f834;
+	mul.f32 	%f837, %f1064, %f1101;
+	mul.f32 	%f838, %f1063, %f1102;
+	sub.f32 	%f839, %f838, %f837;
+	setp.lt.u32	%p132, %r96, 16777216;
+	selp.f32	%f840, 0fBF800000, 0f3F800000, %p132;
+	mul.f32 	%f841, %f833, %f840;
+	mul.f32 	%f842, %f836, %f840;
+	mul.f32 	%f843, %f839, %f840;
+	mul.f32 	%f844, %f841, 0f3F3504F3;
+	mul.f32 	%f845, %f842, 0f3F3504F3;
+	mul.f32 	%f846, %f843, 0f3F3504F3;
+	fma.rn.f32 	%f847, %f1101, 0fBED105EC, %f844;
+	fma.rn.f32 	%f848, %f1102, 0fBED105EC, %f845;
+	fma.rn.f32 	%f849, %f1103, 0fBED105EC, %f846;
+	add.f32 	%f163, %f151, %f847;
+	add.f32 	%f164, %f153, %f848;
+	add.f32 	%f165, %f155, %f849;
+	ld.global.v2.u32 	{%r313, %r314}, [pixelID];
+	cvt.u64.u32	%rd108, %r313;
+	cvt.u64.u32	%rd109, %r314;
+	// inline asm
+	call (%rd106), _rt_buffer_get_64, (%rd93, %r105, %r377, %rd108, %rd109, %rd30, %rd30);
+	// inline asm
+	ld.u32 	%r98, [%rd106];
+	shr.u32 	%r99, %r98, 16;
+	cvt.u16.u32	%rs51, %r99;
+	and.b16  	%rs52, %rs51, 255;
+	cvt.u16.u32	%rs53, %r98;
+	or.b16  	%rs54, %rs53, %rs52;
+	setp.eq.s16	%p133, %rs54, 0;
+	mov.f32 	%f1105, %f1104;
+	mov.f32 	%f1106, %f1104;
+	@%p133 bra 	BB0_126;
+
+	ld.u8 	%rs55, [%rd106+1];
+	and.b16  	%rs57, %rs53, 255;
+	cvt.rn.f32.u16	%f850, %rs57;
+	div.rn.f32 	%f851, %f850, 0f437F0000;
+	fma.rn.f32 	%f852, %f851, 0f40000000, 0fBF800000;
+	cvt.rn.f32.u16	%f853, %rs55;
+	div.rn.f32 	%f854, %f853, 0f437F0000;
+	fma.rn.f32 	%f855, %f854, 0f40000000, 0fBF800000;
+	cvt.rn.f32.u16	%f856, %rs52;
+	div.rn.f32 	%f857, %f856, 0f437F0000;
+	fma.rn.f32 	%f858, %f857, 0f40000000, 0fBF800000;
+	mul.f32 	%f859, %f855, %f855;
+	fma.rn.f32 	%f860, %f852, %f852, %f859;
+	fma.rn.f32 	%f861, %f858, %f858, %f860;
+	sqrt.rn.f32 	%f862, %f861;
+	rcp.rn.f32 	%f863, %f862;
+	mul.f32 	%f1104, %f852, %f863;
+	mul.f32 	%f1105, %f855, %f863;
+	mul.f32 	%f1106, %f858, %f863;
+
+BB0_126:
+	mul.f32 	%f865, %f1065, %f1105;
+	mul.f32 	%f866, %f1064, %f1106;
+	sub.f32 	%f867, %f866, %f865;
+	mul.f32 	%f868, %f1063, %f1106;
+	mul.f32 	%f869, %f1065, %f1104;
+	sub.f32 	%f870, %f869, %f868;
+	mul.f32 	%f871, %f1064, %f1104;
+	mul.f32 	%f872, %f1063, %f1105;
+	sub.f32 	%f873, %f872, %f871;
+	setp.lt.u32	%p134, %r98, 16777216;
+	selp.f32	%f874, 0fBF800000, 0f3F800000, %p134;
+	mul.f32 	%f875, %f867, %f874;
+	mul.f32 	%f876, %f870, %f874;
+	mul.f32 	%f877, %f873, %f874;
+	mul.f32 	%f878, %f875, 0fBF3504F3;
+	mul.f32 	%f879, %f876, 0fBF3504F3;
+	mul.f32 	%f880, %f877, 0fBF3504F3;
+	fma.rn.f32 	%f881, %f1104, 0fBED105EC, %f878;
+	fma.rn.f32 	%f882, %f1105, 0fBED105EC, %f879;
+	fma.rn.f32 	%f883, %f1106, 0fBED105EC, %f880;
+	add.f32 	%f884, %f151, %f881;
+	add.f32 	%f885, %f153, %f882;
+	add.f32 	%f886, %f155, %f883;
+	ld.global.f32 	%f887, [directDir];
+	mul.f32 	%f888, %f152, %f887;
+	ld.global.f32 	%f889, [directDir+4];
+	mul.f32 	%f890, %f154, %f889;
+	neg.f32 	%f891, %f890;
+	sub.f32 	%f892, %f891, %f888;
+	ld.global.f32 	%f893, [directDir+8];
+	mul.f32 	%f894, %f156, %f893;
+	sub.f32 	%f895, %f892, %f894;
+	cvt.sat.f32.f32	%f896, %f895;
+	mul.f32 	%f897, %f90, %f896;
+	mul.f32 	%f898, %f91, %f896;
+	mul.f32 	%f899, %f92, %f896;
+	mul.f32 	%f900, %f163, %f887;
+	mul.f32 	%f901, %f164, %f889;
+	neg.f32 	%f902, %f901;
+	sub.f32 	%f903, %f902, %f900;
+	mul.f32 	%f904, %f165, %f893;
+	sub.f32 	%f905, %f903, %f904;
+	cvt.sat.f32.f32	%f906, %f905;
+	mul.f32 	%f907, %f90, %f906;
+	mul.f32 	%f908, %f91, %f906;
+	mul.f32 	%f909, %f92, %f906;
+	mul.f32 	%f910, %f884, %f887;
+	mul.f32 	%f911, %f885, %f889;
+	neg.f32 	%f912, %f911;
+	sub.f32 	%f913, %f912, %f910;
+	mul.f32 	%f914, %f886, %f893;
+	sub.f32 	%f915, %f913, %f914;
+	cvt.sat.f32.f32	%f916, %f915;
+	mul.f32 	%f917, %f90, %f916;
+	mul.f32 	%f918, %f91, %f916;
+	mul.f32 	%f919, %f92, %f916;
+	add.f32 	%f920, %f897, %f907;
+	add.f32 	%f921, %f898, %f908;
+	add.f32 	%f922, %f899, %f909;
+	add.f32 	%f923, %f920, %f917;
+	add.f32 	%f924, %f921, %f918;
+	add.f32 	%f925, %f922, %f919;
+	mul.f32 	%f926, %f923, 0f3F13CD3A;
+	mul.f32 	%f927, %f924, 0f3F13CD3A;
+	mul.f32 	%f928, %f925, 0f3F13CD3A;
+	div.rn.f32 	%f929, %f73, %f926;
+	div.rn.f32 	%f930, %f74, %f927;
+	div.rn.f32 	%f931, %f75, %f928;
+	setp.eq.f32	%p135, %f73, 0f00000000;
+	selp.f32	%f932, 0f00000000, %f929, %p135;
+	setp.eq.f32	%p136, %f74, 0f00000000;
+	selp.f32	%f933, 0f00000000, %f930, %p136;
+	setp.eq.f32	%p137, %f75, 0f00000000;
+	selp.f32	%f934, 0f00000000, %f931, %p137;
+	mul.f32 	%f172, %f897, %f932;
+	mul.f32 	%f173, %f898, %f933;
+	mul.f32 	%f174, %f899, %f934;
+	mul.f32 	%f175, %f907, %f932;
+	mul.f32 	%f176, %f908, %f933;
+	mul.f32 	%f177, %f909, %f934;
+	mul.f32 	%f178, %f917, %f932;
+	mul.f32 	%f179, %f918, %f933;
+	mul.f32 	%f180, %f919, %f934;
+	ld.global.u32 	%r317, [additive];
+	setp.eq.s32	%p138, %r317, 0;
+	cvt.u64.u32	%rd21, %r2;
+	cvt.u64.u32	%rd22, %r3;
+	mov.f32 	%f864, 0f3F800000;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs60, %f864;}
+
+	// inline asm
+	@%p138 bra 	BB0_128;
+
+	mov.u64 	%rd125, image_RNM0;
+	cvta.global.u64 	%rd114, %rd125;
+	mov.u32 	%r321, 8;
+	// inline asm
+	call (%rd113), _rt_buffer_get_64, (%rd114, %r105, %r321, %rd21, %rd22, %rd30, %rd30);
+	// inline asm
+	ld.v4.u16 	{%rs67, %rs68, %rs69, %rs70}, [%rd113];
+	// inline asm
+	{  cvt.f32.f16 %f935, %rs67;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f936, %rs68;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f937, %rs69;}
+
+	// inline asm
+	// inline asm
+	call (%rd119), _rt_buffer_get_64, (%rd114, %r105, %r321, %rd21, %rd22, %rd30, %rd30);
+	// inline asm
+	add.f32 	%f938, %f172, %f935;
+	add.f32 	%f939, %f173, %f936;
+	add.f32 	%f940, %f174, %f937;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs66, %f940;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs65, %f939;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs64, %f938;}
+
+	// inline asm
+	st.v4.u16 	[%rd119], {%rs64, %rs65, %rs66, %rs60};
+	bra.uni 	BB0_129;
+
+BB0_128:
+	mov.u64 	%rd132, image_RNM0;
+	cvta.global.u64 	%rd127, %rd132;
+	mov.u32 	%r323, 8;
+	// inline asm
+	call (%rd126), _rt_buffer_get_64, (%rd127, %r105, %r323, %rd21, %rd22, %rd30, %rd30);
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs73, %f174;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs72, %f173;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs71, %f172;}
+
+	// inline asm
+	st.v4.u16 	[%rd126], {%rs71, %rs72, %rs73, %rs60};
+
+BB0_129:
+	ld.global.u32 	%r324, [additive];
+	setp.eq.s32	%p139, %r324, 0;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs74, %f864;}
+
+	// inline asm
+	@%p139 bra 	BB0_131;
+
+	mov.u64 	%rd145, image_RNM1;
+	cvta.global.u64 	%rd134, %rd145;
+	mov.u32 	%r328, 8;
+	// inline asm
+	call (%rd133), _rt_buffer_get_64, (%rd134, %r105, %r328, %rd21, %rd22, %rd30, %rd30);
+	// inline asm
+	ld.v4.u16 	{%rs81, %rs82, %rs83, %rs84}, [%rd133];
+	// inline asm
+	{  cvt.f32.f16 %f945, %rs81;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f946, %rs82;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f947, %rs83;}
+
+	// inline asm
+	// inline asm
+	call (%rd139), _rt_buffer_get_64, (%rd134, %r105, %r328, %rd21, %rd22, %rd30, %rd30);
+	// inline asm
+	add.f32 	%f948, %f175, %f945;
+	add.f32 	%f949, %f176, %f946;
+	add.f32 	%f950, %f177, %f947;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs80, %f950;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs79, %f949;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs78, %f948;}
+
+	// inline asm
+	st.v4.u16 	[%rd139], {%rs78, %rs79, %rs80, %rs74};
+	bra.uni 	BB0_132;
+
+BB0_131:
+	mov.u64 	%rd152, image_RNM1;
+	cvta.global.u64 	%rd147, %rd152;
+	mov.u32 	%r330, 8;
+	// inline asm
+	call (%rd146), _rt_buffer_get_64, (%rd147, %r105, %r330, %rd21, %rd22, %rd30, %rd30);
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs87, %f177;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs86, %f176;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs85, %f175;}
+
+	// inline asm
+	st.v4.u16 	[%rd146], {%rs85, %rs86, %rs87, %rs74};
+
+BB0_132:
+	ld.global.u32 	%r331, [additive];
+	setp.eq.s32	%p140, %r331, 0;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs88, %f864;}
+
+	// inline asm
+	@%p140 bra 	BB0_134;
+
+	mov.u64 	%rd165, image_RNM2;
+	cvta.global.u64 	%rd154, %rd165;
+	mov.u32 	%r335, 8;
+	// inline asm
+	call (%rd153), _rt_buffer_get_64, (%rd154, %r105, %r335, %rd21, %rd22, %rd30, %rd30);
+	// inline asm
+	ld.v4.u16 	{%rs95, %rs96, %rs97, %rs98}, [%rd153];
+	// inline asm
+	{  cvt.f32.f16 %f955, %rs95;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f956, %rs96;}
+
+	// inline asm
+	// inline asm
+	{  cvt.f32.f16 %f957, %rs97;}
+
+	// inline asm
+	// inline asm
+	call (%rd159), _rt_buffer_get_64, (%rd154, %r105, %r335, %rd21, %rd22, %rd30, %rd30);
+	// inline asm
+	add.f32 	%f958, %f178, %f955;
+	add.f32 	%f959, %f179, %f956;
+	add.f32 	%f960, %f180, %f957;
+	// inline asm
+	{  cvt.rn.f16.f32 %rs94, %f960;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs93, %f959;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs92, %f958;}
+
+	// inline asm
+	st.v4.u16 	[%rd159], {%rs92, %rs93, %rs94, %rs88};
+	bra.uni 	BB0_152;
+
+BB0_134:
+	mov.u64 	%rd172, image_RNM2;
+	cvta.global.u64 	%rd167, %rd172;
+	mov.u32 	%r337, 8;
+	// inline asm
+	call (%rd166), _rt_buffer_get_64, (%rd167, %r105, %r337, %rd21, %rd22, %rd30, %rd30);
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs101, %f180;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs100, %f179;}
+
+	// inline asm
+	// inline asm
+	{  cvt.rn.f16.f32 %rs99, %f178;}
+
+	// inline asm
+	st.v4.u16 	[%rd166], {%rs99, %rs100, %rs101, %rs88};
+
+BB0_152:
+	ret;
+}
+
+