summaryrefslogtreecommitdiff
path: root/VRCSDK3Worlds/Assets/Editor/x64/Bakery/dilate.ptx
diff options
context:
space:
mode:
authortylermurphy534 <tylermurphy534@gmail.com>2022-11-06 15:12:42 -0500
committertylermurphy534 <tylermurphy534@gmail.com>2022-11-06 15:12:42 -0500
commiteb84bb298d2b95aec7b2ae12cbf25ac64f25379a (patch)
treeefd616a157df06ab661c6d56651853431ac6b08b /VRCSDK3Worlds/Assets/Editor/x64/Bakery/dilate.ptx
downloadunityprojects-eb84bb298d2b95aec7b2ae12cbf25ac64f25379a.tar.gz
unityprojects-eb84bb298d2b95aec7b2ae12cbf25ac64f25379a.tar.bz2
unityprojects-eb84bb298d2b95aec7b2ae12cbf25ac64f25379a.zip
move to self host
Diffstat (limited to 'VRCSDK3Worlds/Assets/Editor/x64/Bakery/dilate.ptx')
-rw-r--r--VRCSDK3Worlds/Assets/Editor/x64/Bakery/dilate.ptx473
1 files changed, 473 insertions, 0 deletions
diff --git a/VRCSDK3Worlds/Assets/Editor/x64/Bakery/dilate.ptx b/VRCSDK3Worlds/Assets/Editor/x64/Bakery/dilate.ptx
new file mode 100644
index 00000000..b903d35c
--- /dev/null
+++ b/VRCSDK3Worlds/Assets/Editor/x64/Bakery/dilate.ptx
@@ -0,0 +1,473 @@
+//
+// Generated by NVIDIA NVVM Compiler
+//
+// Compiler Build ID: CL-23083092
+// Cuda compilation tools, release 9.1, V9.1.85
+// Based on LLVM 3.4svn
+//
+
+.version 6.1
+.target sm_30
+.address_size 64
+
+ // .globl _Z6oxMainv
+.global .align 8 .b8 pixelID[8];
+.global .align 8 .b8 resolution[8];
+.global .align 4 .b8 normal[12];
+.global .align 4 .b8 camPos[12];
+.global .align 4 .b8 root[4];
+.global .align 4 .u32 imageEnabled;
+.global .texref lightmap;
+.global .align 16 .b8 tileInfo[16];
+.global .align 4 .u32 additive;
+.global .align 1 .b8 image[1];
+.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo6normalE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo6camPosE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo4rootE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo12imageEnabledE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo8tileInfoE[8] = {82, 97, 121, 0, 16, 0, 0, 0};
+.global .align 4 .b8 _ZN21rti_internal_typeinfo8additiveE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
+.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E;
+.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E;
+.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E;
+.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE;
+.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE;
+.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE;
+.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename6normalE[7] = {102, 108, 111, 97, 116, 51, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename6camPosE[7] = {102, 108, 111, 97, 116, 51, 0};
+.global .align 16 .b8 _ZN21rti_internal_typename4rootE[9] = {114, 116, 79, 98, 106, 101, 99, 116, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename12imageEnabledE[4] = {105, 110, 116, 0};
+.global .align 8 .b8 _ZN21rti_internal_typename8tileInfoE[6] = {117, 105, 110, 116, 52, 0};
+.global .align 4 .b8 _ZN21rti_internal_typename8additiveE[4] = {105, 110, 116, 0};
+.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum6normalE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum6camPosE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum4rootE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum12imageEnabledE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum8tileInfoE = 4919;
+.global .align 4 .u32 _ZN21rti_internal_typeenum8additiveE = 4919;
+.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0};
+.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0};
+.global .align 16 .b8 _ZN21rti_internal_semantic6normalE[17] = {97, 116, 116, 114, 105, 98, 117, 116, 101, 32, 110, 111, 114, 109, 97, 108, 0};
+.global .align 1 .b8 _ZN21rti_internal_semantic6camPosE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic4rootE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic12imageEnabledE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic8tileInfoE[1];
+.global .align 1 .b8 _ZN21rti_internal_semantic8additiveE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation6normalE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation6camPosE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation4rootE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation12imageEnabledE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation8tileInfoE[1];
+.global .align 1 .b8 _ZN23rti_internal_annotation8additiveE[1];
+
+.visible .entry _Z6oxMainv(
+
+)
+{
+ .reg .pred %p<14>;
+ .reg .b16 %rs<45>;
+ .reg .f32 %f<159>;
+ .reg .b32 %r<149>;
+ .reg .b64 %rd<271>;
+
+
+ ld.global.v2.u32 {%r18, %r19}, [pixelID];
+ cvt.u64.u32 %rd9, %r18;
+ cvt.u64.u32 %rd10, %r19;
+ mov.u64 %rd13, image;
+ cvta.global.u64 %rd8, %rd13;
+ mov.u32 %r16, 2;
+ mov.u32 %r17, 4;
+ mov.u64 %rd12, 0;
+ // inline asm
+ call (%rd7), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd9, %rd10, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs1, [%rd7+3];
+ setp.ne.s16 %p1, %rs1, 0;
+ @%p1 bra BB0_17;
+
+ ld.global.v2.u32 {%r33, %r34}, [pixelID];
+ cvt.u64.u32 %rd16, %r33;
+ cvt.u64.u32 %rd17, %r34;
+ // inline asm
+ call (%rd14), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd16, %rd17, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs2, [%rd14+2];
+ cvt.rn.f32.u16 %f61, %rs2;
+ div.rn.f32 %f135, %f61, 0f437F0000;
+ ld.global.v2.u32 {%r37, %r38}, [pixelID];
+ cvt.u64.u32 %rd22, %r37;
+ cvt.u64.u32 %rd23, %r38;
+ // inline asm
+ call (%rd20), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd22, %rd23, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs3, [%rd20+1];
+ cvt.rn.f32.u16 %f62, %rs3;
+ div.rn.f32 %f136, %f62, 0f437F0000;
+ ld.global.v2.u32 {%r41, %r42}, [pixelID];
+ cvt.u64.u32 %rd28, %r41;
+ cvt.u64.u32 %rd29, %r42;
+ // inline asm
+ call (%rd26), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd28, %rd29, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs4, [%rd26];
+ cvt.rn.f32.u16 %f63, %rs4;
+ div.rn.f32 %f137, %f63, 0f437F0000;
+ ld.global.v2.u32 {%r45, %r46}, [pixelID];
+ cvt.u64.u32 %rd34, %r45;
+ cvt.u64.u32 %rd35, %r46;
+ // inline asm
+ call (%rd32), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd34, %rd35, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs5, [%rd32+3];
+ cvt.rn.f32.u16 %f64, %rs5;
+ div.rn.f32 %f138, %f64, 0f437F0000;
+ ld.global.v2.u32 {%r49, %r50}, [pixelID];
+ setp.eq.s32 %p2, %r49, 0;
+ add.s32 %r52, %r49, -1;
+ cvt.u64.u32 %rd45, %r52;
+ selp.b64 %rd40, 0, %rd45, %p2;
+ setp.eq.s32 %p3, %r50, 0;
+ add.s32 %r54, %r50, -1;
+ cvt.u64.u32 %rd46, %r54;
+ selp.b64 %rd41, 0, %rd46, %p3;
+ ld.global.v2.u32 {%r55, %r56}, [resolution];
+ add.s32 %r58, %r55, -1;
+ setp.eq.s32 %p4, %r49, %r58;
+ add.s32 %r59, %r49, 1;
+ selp.b32 %r1, %r58, %r59, %p4;
+ add.s32 %r61, %r56, -1;
+ setp.eq.s32 %p5, %r50, %r61;
+ add.s32 %r62, %r50, 1;
+ selp.b32 %r2, %r61, %r62, %p5;
+ // inline asm
+ call (%rd38), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs6, [%rd38+3];
+ setp.eq.s16 %p6, %rs6, 0;
+ mov.u32 %r143, 0;
+ @%p6 bra BB0_3;
+
+ // inline asm
+ call (%rd47), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs7, [%rd47+2];
+ cvt.rn.f32.u16 %f65, %rs7;
+ div.rn.f32 %f66, %f65, 0f437F0000;
+ // inline asm
+ call (%rd53), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs8, [%rd53+1];
+ cvt.rn.f32.u16 %f67, %rs8;
+ div.rn.f32 %f68, %f67, 0f437F0000;
+ // inline asm
+ call (%rd59), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs9, [%rd59];
+ cvt.rn.f32.u16 %f69, %rs9;
+ div.rn.f32 %f70, %f69, 0f437F0000;
+ // inline asm
+ call (%rd65), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs10, [%rd65+3];
+ cvt.rn.f32.u16 %f71, %rs10;
+ div.rn.f32 %f72, %f71, 0f437F0000;
+ add.f32 %f135, %f135, %f66;
+ add.f32 %f136, %f136, %f68;
+ add.f32 %f137, %f137, %f70;
+ add.f32 %f138, %f138, %f72;
+ mov.u32 %r143, 1;
+
+BB0_3:
+ ld.global.u32 %rd74, [pixelID];
+ // inline asm
+ call (%rd72), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd74, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs11, [%rd72+3];
+ setp.eq.s16 %p7, %rs11, 0;
+ @%p7 bra BB0_5;
+
+ // inline asm
+ call (%rd79), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd74, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs12, [%rd79+2];
+ cvt.rn.f32.u16 %f73, %rs12;
+ div.rn.f32 %f74, %f73, 0f437F0000;
+ // inline asm
+ call (%rd85), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd74, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs13, [%rd85+1];
+ cvt.rn.f32.u16 %f75, %rs13;
+ div.rn.f32 %f76, %f75, 0f437F0000;
+ // inline asm
+ call (%rd91), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd74, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs14, [%rd91];
+ cvt.rn.f32.u16 %f77, %rs14;
+ div.rn.f32 %f78, %f77, 0f437F0000;
+ // inline asm
+ call (%rd97), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd74, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs15, [%rd97+3];
+ cvt.rn.f32.u16 %f79, %rs15;
+ div.rn.f32 %f80, %f79, 0f437F0000;
+ add.f32 %f135, %f135, %f74;
+ add.f32 %f136, %f136, %f76;
+ add.f32 %f137, %f137, %f78;
+ add.f32 %f138, %f138, %f80;
+ add.s32 %r143, %r143, 1;
+
+BB0_5:
+ cvt.u64.u32 %rd106, %r1;
+ // inline asm
+ call (%rd104), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs16, [%rd104+3];
+ setp.eq.s16 %p8, %rs16, 0;
+ @%p8 bra BB0_7;
+
+ // inline asm
+ call (%rd111), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs17, [%rd111+2];
+ cvt.rn.f32.u16 %f81, %rs17;
+ div.rn.f32 %f82, %f81, 0f437F0000;
+ // inline asm
+ call (%rd117), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs18, [%rd117+1];
+ cvt.rn.f32.u16 %f83, %rs18;
+ div.rn.f32 %f84, %f83, 0f437F0000;
+ // inline asm
+ call (%rd123), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs19, [%rd123];
+ cvt.rn.f32.u16 %f85, %rs19;
+ div.rn.f32 %f86, %f85, 0f437F0000;
+ // inline asm
+ call (%rd129), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd41, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs20, [%rd129+3];
+ cvt.rn.f32.u16 %f87, %rs20;
+ div.rn.f32 %f88, %f87, 0f437F0000;
+ add.f32 %f135, %f135, %f82;
+ add.f32 %f136, %f136, %f84;
+ add.f32 %f137, %f137, %f86;
+ add.f32 %f138, %f138, %f88;
+ add.s32 %r143, %r143, 1;
+
+BB0_7:
+ ld.global.u32 %rd139, [pixelID+4];
+ // inline asm
+ call (%rd136), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd139, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs21, [%rd136+3];
+ setp.eq.s16 %p9, %rs21, 0;
+ @%p9 bra BB0_9;
+
+ // inline asm
+ call (%rd143), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd139, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs22, [%rd143+2];
+ cvt.rn.f32.u16 %f89, %rs22;
+ div.rn.f32 %f90, %f89, 0f437F0000;
+ // inline asm
+ call (%rd149), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd139, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs23, [%rd149+1];
+ cvt.rn.f32.u16 %f91, %rs23;
+ div.rn.f32 %f92, %f91, 0f437F0000;
+ // inline asm
+ call (%rd155), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd139, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs24, [%rd155];
+ cvt.rn.f32.u16 %f93, %rs24;
+ div.rn.f32 %f94, %f93, 0f437F0000;
+ // inline asm
+ call (%rd161), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd139, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs25, [%rd161+3];
+ cvt.rn.f32.u16 %f95, %rs25;
+ div.rn.f32 %f96, %f95, 0f437F0000;
+ add.f32 %f135, %f135, %f90;
+ add.f32 %f136, %f136, %f92;
+ add.f32 %f137, %f137, %f94;
+ add.f32 %f138, %f138, %f96;
+ add.s32 %r143, %r143, 1;
+
+BB0_9:
+ // inline asm
+ call (%rd168), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd139, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs26, [%rd168+3];
+ setp.eq.s16 %p10, %rs26, 0;
+ @%p10 bra BB0_11;
+
+ // inline asm
+ call (%rd175), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd139, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs27, [%rd175+2];
+ cvt.rn.f32.u16 %f97, %rs27;
+ div.rn.f32 %f98, %f97, 0f437F0000;
+ // inline asm
+ call (%rd181), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd139, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs28, [%rd181+1];
+ cvt.rn.f32.u16 %f99, %rs28;
+ div.rn.f32 %f100, %f99, 0f437F0000;
+ // inline asm
+ call (%rd187), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd139, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs29, [%rd187];
+ cvt.rn.f32.u16 %f101, %rs29;
+ div.rn.f32 %f102, %f101, 0f437F0000;
+ // inline asm
+ call (%rd193), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd139, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs30, [%rd193+3];
+ cvt.rn.f32.u16 %f103, %rs30;
+ div.rn.f32 %f104, %f103, 0f437F0000;
+ add.f32 %f135, %f135, %f98;
+ add.f32 %f136, %f136, %f100;
+ add.f32 %f137, %f137, %f102;
+ add.f32 %f138, %f138, %f104;
+ add.s32 %r143, %r143, 1;
+
+BB0_11:
+ cvt.u64.u32 %rd203, %r2;
+ // inline asm
+ call (%rd200), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd203, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs31, [%rd200+3];
+ setp.eq.s16 %p11, %rs31, 0;
+ @%p11 bra BB0_13;
+
+ // inline asm
+ call (%rd207), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd203, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs32, [%rd207+2];
+ cvt.rn.f32.u16 %f105, %rs32;
+ div.rn.f32 %f106, %f105, 0f437F0000;
+ // inline asm
+ call (%rd213), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd203, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs33, [%rd213+1];
+ cvt.rn.f32.u16 %f107, %rs33;
+ div.rn.f32 %f108, %f107, 0f437F0000;
+ // inline asm
+ call (%rd219), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd203, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs34, [%rd219];
+ cvt.rn.f32.u16 %f109, %rs34;
+ div.rn.f32 %f110, %f109, 0f437F0000;
+ // inline asm
+ call (%rd225), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd40, %rd203, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs35, [%rd225+3];
+ cvt.rn.f32.u16 %f111, %rs35;
+ div.rn.f32 %f112, %f111, 0f437F0000;
+ add.f32 %f135, %f135, %f106;
+ add.f32 %f136, %f136, %f108;
+ add.f32 %f137, %f137, %f110;
+ add.f32 %f138, %f138, %f112;
+ add.s32 %r143, %r143, 1;
+
+BB0_13:
+ // inline asm
+ call (%rd232), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd203, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs36, [%rd232+3];
+ setp.eq.s16 %p12, %rs36, 0;
+ @%p12 bra BB0_15;
+
+ // inline asm
+ call (%rd239), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd203, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs37, [%rd239+2];
+ cvt.rn.f32.u16 %f113, %rs37;
+ div.rn.f32 %f114, %f113, 0f437F0000;
+ // inline asm
+ call (%rd245), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd203, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs38, [%rd245+1];
+ cvt.rn.f32.u16 %f115, %rs38;
+ div.rn.f32 %f116, %f115, 0f437F0000;
+ // inline asm
+ call (%rd251), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd203, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs39, [%rd251];
+ cvt.rn.f32.u16 %f117, %rs39;
+ div.rn.f32 %f118, %f117, 0f437F0000;
+ // inline asm
+ call (%rd257), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd106, %rd203, %rd12, %rd12);
+ // inline asm
+ ld.u8 %rs40, [%rd257+3];
+ cvt.rn.f32.u16 %f119, %rs40;
+ div.rn.f32 %f120, %f119, 0f437F0000;
+ add.f32 %f135, %f135, %f114;
+ add.f32 %f136, %f136, %f116;
+ add.f32 %f137, %f137, %f118;
+ add.f32 %f138, %f138, %f120;
+ add.s32 %r143, %r143, 1;
+
+BB0_15:
+ setp.eq.s32 %p13, %r143, 0;
+ @%p13 bra BB0_17;
+
+ cvt.rn.f32.u32 %f121, %r143;
+ rcp.rn.f32 %f122, %f121;
+ mul.f32 %f123, %f135, %f122;
+ mul.f32 %f124, %f136, %f122;
+ mul.f32 %f125, %f137, %f122;
+ mul.f32 %f126, %f138, %f122;
+ mul.f32 %f127, %f123, 0f437F0000;
+ mul.f32 %f128, %f124, 0f437F0000;
+ mul.f32 %f129, %f125, 0f437F0000;
+ mul.f32 %f130, %f126, 0f437F0000;
+ ld.global.v2.u32 {%r134, %r135}, [pixelID];
+ cvt.u64.u32 %rd266, %r134;
+ cvt.u64.u32 %rd267, %r135;
+ // inline asm
+ call (%rd264), _rt_buffer_get_64, (%rd8, %r16, %r17, %rd266, %rd267, %rd12, %rd12);
+ // inline asm
+ cvt.rzi.u32.f32 %r138, %f129;
+ cvt.rzi.u32.f32 %r139, %f128;
+ cvt.rzi.u32.f32 %r140, %f127;
+ cvt.rzi.u32.f32 %r141, %f130;
+ cvt.u16.u32 %rs41, %r141;
+ cvt.u16.u32 %rs42, %r140;
+ cvt.u16.u32 %rs43, %r139;
+ cvt.u16.u32 %rs44, %r138;
+ st.v4.u8 [%rd264], {%rs44, %rs43, %rs42, %rs41};
+
+BB0_17:
+ ret;
+}
+
+