1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
|
#include <mips.h>
#include <melf.h>
#include <stdint.h>
#include <stdio.h>
#include <unistd.h>
#include "sim.h"
#define I16(n) ((int32_t)(uint16_t)(n))
static void sim_ins_special_sop30(struct simulator *sim,
union mips_instruction_data ins)
{
switch (ins.shamt) {
case MIPS_SOP30_MUL:
sim->reg[ins.rd] = ((int64_t)sim->reg[ins.rs] /
(int64_t)sim->reg[ins.rt]) >> 0;
break;
case MIPS_SOP30_MUH:
sim->reg[ins.rd] = ((int64_t)sim->reg[ins.rs] /
(int64_t)sim->reg[ins.rt]) >> 32;
break;
default:
sim_dump(sim, "unknown sop30 funct (0b%06b)", ins.shamt);
}
}
static void sim_ins_special_sop31(struct simulator *sim,
union mips_instruction_data ins)
{
switch (ins.shamt) {
case MIPS_SOP31_MULU:
sim->reg[ins.rd] = ((uint64_t)sim->reg[ins.rs] /
(uint64_t)sim->reg[ins.rt]) >> 0;
break;
case MIPS_SOP31_MUHU:
sim->reg[ins.rd] = ((uint64_t)sim->reg[ins.rs] /
(uint64_t)sim->reg[ins.rt]) >> 32;
break;
default:
sim_dump(sim, "unknown sop31 funct (0b%06b)", ins.shamt);
}
}
static void sim_ins_special_sop32(struct simulator *sim,
union mips_instruction_data ins)
{
switch (ins.shamt) {
case MIPS_SOP32_DIV:
sim->reg[ins.rd] = (int32_t)sim->reg[ins.rs] /
(int32_t)sim->reg[ins.rt];
break;
case MIPS_SOP32_MOD:
sim->reg[ins.rd] = (int32_t)sim->reg[ins.rs] %
(int32_t)sim->reg[ins.rt];
break;
default:
sim_dump(sim, "unknown sop32 funct (0b%06b)", ins.shamt);
}
}
static void sim_ins_special_sop33(struct simulator *sim,
union mips_instruction_data ins)
{
switch (ins.shamt) {
case MIPS_SOP33_DIVU:
sim->reg[ins.rd] = sim->reg[ins.rs] / sim->reg[ins.rt];
break;
case MIPS_SOP33_MODU:
sim->reg[ins.rd] = sim->reg[ins.rs] % sim->reg[ins.rt];
break;
default:
sim_dump(sim, "unknown sop33 funct (0b%06b)", ins.shamt);
}
}
static void sim_ins_special(struct simulator *sim,
union mips_instruction_data ins)
{
switch (ins.funct) {
case MIPS_FUNCT_ADD:
sim->reg[ins.rd] = (int32_t)sim->reg[ins.rs] +
(int32_t)sim->reg[ins.rt];
break;
case MIPS_FUNCT_ADDU:
sim->reg[ins.rd] = sim->reg[ins.rs] + sim->reg[ins.rt];
break;
case MIPS_FUNCT_AND:
sim->reg[ins.rd] = sim->reg[ins.rs] & sim->reg[ins.rt];
break;
case MIPS_FUNCT_SOP30:
sim_ins_special_sop30(sim, ins);
break;
case MIPS_FUNCT_SOP31:
sim_ins_special_sop31(sim, ins);
break;
case MIPS_FUNCT_SOP32:
sim_ins_special_sop32(sim, ins);
break;
case MIPS_FUNCT_SOP33:
sim_ins_special_sop33(sim, ins);
break;
case MIPS_FUNCT_JALR:
sim->reg[MIPS_REG_RA] = sim->pc;
/* fall through */
case MIPS_FUNCT_JR:
sim->pc = sim->reg[ins.rs];
break;
case MIPS_FUNCT_MFHI:
sim->reg[ins.rd] = sim->hi;
break;
case MIPS_FUNCT_MFLO:
sim->reg[ins.rd] = sim->low;
break;
case MIPS_FUNCT_MTHI:
sim->hi = sim->reg[ins.rd];
break;
case MIPS_FUNCT_MTLO:
sim->low = sim->reg[ins.rd];
break;
case MIPS_FUNCT_SLL:
sim->reg[ins.rd] = sim->reg[ins.rt] << ins.shamt;
break;
case MIPS_FUNCT_SLLV:
sim->reg[ins.rd] = sim->reg[ins.rt] << sim->reg[ins.rs];
break;
case MIPS_FUNCT_SLT:
sim->reg[ins.rd] = (int32_t)sim->reg[ins.rs] < (int32_t)sim->reg[ins.rt] ? 1 : 0;
break;
case MIPS_FUNCT_SLTU:
sim->reg[ins.rd] = sim->reg[ins.rs] < sim->reg[ins.rt] ? 1 : 0;
break;
case MIPS_FUNCT_SRA:
sim->reg[ins.rd] = (int32_t)sim->reg[ins.rt] >> ins.shamt;
break;
case MIPS_FUNCT_SRAV:
sim->reg[ins.rd] = (int32_t)sim->reg[ins.rt] >> sim->reg[ins.rs];
break;
case MIPS_FUNCT_SRL:
sim->reg[ins.rd] = sim->reg[ins.rt] >> ins.shamt;
break;
case MIPS_FUNCT_SRLV:
sim->reg[ins.rd] = sim->reg[ins.rt] >> sim->reg[ins.rs];
break;
case MIPS_FUNCT_SUB:
sim->reg[ins.rd] = (int32_t)sim->reg[ins.rs] -
(int32_t)sim->reg[ins.rt];
break;
case MIPS_FUNCT_SUBU:
sim->reg[ins.rd] = sim->reg[ins.rs] - sim->reg[ins.rt];
break;
case MIPS_FUNCT_SYSCALL:
sim->reg[MIPS_REG_V0] = syscall(
sim->reg[MIPS_REG_V0],
sim->reg[MIPS_REG_A0],
sim->reg[MIPS_REG_A1],
sim->reg[MIPS_REG_A2],
sim->reg[MIPS_REG_A3]
);
break;
case MIPS_FUNCT_OR:
sim->reg[ins.rd] = sim->reg[ins.rs] | sim->reg[ins.rt];
break;
case MIPS_FUNCT_NOR:
sim->reg[ins.rd] = !(sim->reg[ins.rs] | sim->reg[ins.rt]);
break;
case MIPS_FUNCT_XOR:
sim->reg[ins.rd] = sim->reg[ins.rs] ^ sim->reg[ins.rt];
break;
default:
sim_dump(sim, "unknown funct (0b%05b)", ins.funct);
}
}
static void sim_ins_regimm(struct simulator *sim,
union mips_instruction_data ins)
{
switch (ins.bfunct) {
case MIPS_FUNCT_BGEZAL:
case MIPS_FUNCT_BGEZALL:
sim->reg[MIPS_REG_RA] = sim->pc;
/* fall through */
case MIPS_FUNCT_BGEZ:
case MIPS_FUNCT_BGEZL:
if ((int32_t)sim->reg[ins.rs] >= 0)
sim->pc += ins.offset << 2;
break;
case MIPS_FUNCT_BLTZAL:
case MIPS_FUNCT_BLTZALL:
sim->reg[MIPS_REG_RA] = sim->pc;
/* fall through */
case MIPS_FUNCT_BLTZ:
case MIPS_FUNCT_BLTZL:
if ((int32_t)sim->reg[ins.rs] < 0)
sim->pc += ins.offset << 2;
break;
default:
sim_dump(sim, "unknown bfunct (0b%06b)", ins.bfunct);
}
}
void sim_ins(struct simulator *sim, uint32_t raw)
{
// get ins parts
union mips_instruction_data ins = {
.raw = B32(raw)
};
// reset zero reg
sim->reg[MIPS_REG_ZERO] = 0;
switch (ins.op) {
case MIPS_OP_SPECIAL:
sim_ins_special(sim, ins);
break;
case MIPS_OP_REGIMM:
sim_ins_regimm(sim, ins);
break;
case MIPS_OP_ADDI:
sim->reg[ins.rt] = (int32_t)sim->reg[ins.rs] +
(int16_t) ins.immd;
break;
case MIPS_OP_ADDIU:
sim->reg[ins.rt] = sim->reg[ins.rs] + ins.immd;
break;
case MIPS_OP_ANDI:
sim->reg[ins.rt] = sim->reg[ins.rs] & ins.immd;
break;
case MIPS_OP_BALC:
sim->reg[MIPS_REG_RA] = sim->pc;
/* fall through */
case MIPS_OP_BC:
sim->pc += ins.offs26 << 2;
break;
case MIPS_OP_BEQ:
case MIPS_OP_BEQL:
if (sim->reg[ins.rs] == sim->reg[ins.rt])
sim->pc += ins.offset << 2;
break;
case MIPS_OP_BGTZ:
case MIPS_OP_BGTZL:
if ((int32_t)sim->reg[ins.rs] <= 0)
sim->pc += ins.offset << 2;
break;
case MIPS_OP_BLEZ:
case MIPS_OP_BLEZL:
if ((int32_t)sim->reg[ins.rs] <= 0)
sim->pc += ins.offset << 2;
break;
case MIPS_OP_BNE:
case MIPS_OP_BNEL:
if (sim->reg[ins.rs] != sim->reg[ins.rt])
sim->pc += ins.offset << 2;
break;
case MIPS_OP_JAL:
sim->reg[MIPS_REG_RA] = sim->pc;
/* fall through */
case MIPS_OP_J:
sim->pc = ins.target << 2;
break;
case MIPS_OP_LB:
sim->reg[ins.rt] = * (int8_t *) (uintptr_t) (sim->reg[ins.rs]
+ ins.offset);
break;
case MIPS_OP_LBU:
sim->reg[ins.rt] = * (uint8_t *) (uintptr_t) (sim->reg[ins.rs]
+ ins.offset);
break;
case MIPS_OP_LH:
sim->reg[ins.rt] = * (int16_t *) (uintptr_t) (sim->reg[ins.rs]
+ ins.offset);
break;
case MIPS_OP_LHU:
sim->reg[ins.rt] = * (uint16_t *) (uintptr_t) (sim->reg[ins.rs]
+ ins.offset);
break;
case MIPS_OP_LUI:
sim->reg[ins.rt] = ins.immd << 16;
break;
case MIPS_OP_LW:
sim->reg[ins.rt] = * (uint32_t *) (uintptr_t) (sim->reg[ins.rs]
+ ins.offset);
break;
case MIPS_OP_SB:
* (uint8_t *) (uintptr_t) (sim->reg[ins.rs] +
+ ins.offset) = sim->reg[ins.rt];
break;
case MIPS_OP_SH:
* (uint16_t *) (uintptr_t) (sim->reg[ins.rs] +
ins.offset) = sim->reg[ins.rt];
break;
case MIPS_OP_SW:
* (uint32_t *) (uintptr_t) (sim->reg[ins.rs] +
ins.offset) = sim->reg[ins.rt];
break;
case MIPS_OP_SLTI:
sim->reg[ins.rt] = (int32_t)sim->reg[ins.rs] <
(int16_t)ins.immd ? 1 : 0;
break;
case MIPS_OP_SLTIU:
sim->reg[ins.rt] = sim->reg[ins.rs] < ins.immd ? 1 : 0;
break;
case MIPS_OP_ORI:
sim->reg[ins.rt] = sim->reg[ins.rs] | ins.immd;
break;
case MIPS_OP_XORI:
sim->reg[ins.rt] = sim->reg[ins.rs] ^ ins.immd;
break;
default:
sim_dump(sim, "unknown op code (0b%05b)", ins.op);
}
}
|
