save dev statedev

1 files changed, 305 insertions, 33 deletions

diff --git a/include/mips32r6.h b/include/mips32r6.h
index 88eda4d..c6c1d59 100644
--- a/include/mips32r6.h
+++ b/include/mips32r6.h
@@ -7,6 +7,97 @@
 #include <stdint.h>
 #include <mips.h>
 
+// TODO:
+// balc
+
+// TODO: [add]
+// align
+// aluipc
+// aui
+// auipc
+// bal real ins
+// balc
+// bc
+// bc1eqz
+// bc1nez
+// bc2eqz
+// bc2nez
+// b{le,ge,gt,lt,eq,ne}ZALC
+// b<cond>c
+// bitswap
+// bovc
+// bnvc
+// crc32{b,h,w}
+// c2c32c{b,h,w}
+// div, mod, divu, modu
+// dvp
+// eretnc
+// evp
+// gnvi
+// ginvt
+// jialc
+// jic
+// jr assembly idiom
+// llwp
+// llwpe
+// lsa
+// lwpc
+// mfhc0
+// mthc0
+// mul muh mulu muhu
+// nal
+// scwp
+// scwpe
+// seleqz selnez
+// sigrie
+
+// TODO: [remove]
+// bc1f
+// bc1fl
+// bc1tl
+// bc1tl
+// bc2f
+// bc2fl
+// bc2t
+// bc2tl
+// all branch likely
+// div
+// divu
+// jr
+// ldxc1
+// lui
+// luxc1
+// lwl
+// lwr
+// lwxc1
+// madd
+// maddu
+// mfhi
+// mflo
+// movf
+// movn
+// movt
+// movz
+// msub
+// msubu
+// mthi
+// mtlo
+// mul
+// mult
+// multu
+// prefx
+// sdxc1
+// suxc1
+// swl
+// swr
+// swxc1
+// teqi
+// tgei
+// tgeiu
+// tlti
+// tltiu
+// tnei
+
 /* mips instructions */
 enum mips32r6_instruction_type {
 	MIPS32R6_INS_ADD,
@@ -15,39 +106,110 @@ enum mips32r6_instruction_type {
 	MIPS32R6_INS_ADDU,
 	MIPS32R6_INS_AND,
 	MIPS32R6_INS_ANDI,
-	MIPS32R6_INS_BAL,
-	MIPS32R6_INS_BALC,
-	MIPS32R6_INS_BC,
+	MIPS32R6_INS_BC1F,
+	MIPS32R6_INS_BC1FL,
+	MIPS32R6_INS_BC1T,
+	MIPS32R6_INS_BC1TL,
+	MIPS32R6_INS_BC2F,
+	MIPS32R6_INS_BC2FL,
+	MIPS32R6_INS_BC2T,
+	MIPS32R6_INS_BC2TL,
 	MIPS32R6_INS_BEQ,
+	MIPS32R6_INS_BEQL,
 	MIPS32R6_INS_BGEZ,
 	MIPS32R6_INS_BGEZAL,
+	MIPS32R6_INS_BGEZALL,
+	MIPS32R6_INS_BGEZL,
 	MIPS32R6_INS_BGTZ,
+	MIPS32R6_INS_BGTZL,
 	MIPS32R6_INS_BLEZ,
+	MIPS32R6_INS_BLEZL,
 	MIPS32R6_INS_BLTZ,
 	MIPS32R6_INS_BLTZAL,
+	MIPS32R6_INS_BLTZALL,
+	MIPS32R6_INS_BLTZL,
 	MIPS32R6_INS_BNE,
+	MIPS32R6_INS_BNEL,
+	MIPS32R6_INS_BREAK,
+	MIPS32R6_INS_CACHE,
+	MIPS32R6_INS_CFC1,
+	MIPS32R6_INS_CFC2,
+	MIPS32R6_INS_CLO,
+	MIPS32R6_INS_CLZ,
+	MIPS32R6_INS_COP2,
+	MIPS32R6_INS_CTC1,
+	MIPS32R6_INS_CTC2,
+	MIPS32R6_INS_DERET,
+	MIPS32R6_INS_DI,
 	MIPS32R6_INS_DIV,
-	MIPS32R6_INS_MOD,
 	MIPS32R6_INS_DIVU,
-	MIPS32R6_INS_MODU,
+	MIPS32R6_INS_EI,
+	MIPS32R6_INS_ERET,
+	MIPS32R6_INS_EXT,
+	MIPS32R6_INS_INS,
 	MIPS32R6_INS_J,
 	MIPS32R6_INS_JAL,
 	MIPS32R6_INS_JALR,
-	MIPS32R6_INS_JALX,
 	MIPS32R6_INS_JR,
 	MIPS32R6_INS_LB,
 	MIPS32R6_INS_LBU,
+	MIPS32R6_INS_LDC1,
+	MIPS32R6_INS_LDC2,
+	MIPS32R6_INS_LDXC1,
 	MIPS32R6_INS_LH,
 	MIPS32R6_INS_LHU,
+	MIPS32R6_INS_LL,
 	MIPS32R6_INS_LUI,
+	MIPS32R6_INS_LUXC1,
 	MIPS32R6_INS_LW,
+	MIPS32R6_INS_LWC1,
+	MIPS32R6_INS_LWC2,
+	MIPS32R6_INS_LWL,
+	MIPS32R6_INS_LWR,
+	MIPS32R6_INS_LWXC1,
+	MIPS32R6_INS_MADD,
+	MIPS32R6_INS_MADDU,
+	MIPS32R6_INS_MFC0,
+	MIPS32R6_INS_MFC1,
+	MIPS32R6_INS_MFC2,
+	MIPS32R6_INS_MFHC1,
+	MIPS32R6_INS_MFHC2,
+	MIPS32R6_INS_MFHI,
+	MIPS32R6_INS_MFLO,
+	MIPS32R6_INS_MOVF,
+	MIPS32R6_INS_MOVN,
+	MIPS32R6_INS_MOVT,
+	MIPS32R6_INS_MOVZ,
+	MIPS32R6_INS_MSUB,
+	MIPS32R6_INS_MSUBU,
+	MIPS32R6_INS_MTC0,
+	MIPS32R6_INS_MTC1,
+	MIPS32R6_INS_MTC2,
+	MIPS32R6_INS_MTHC1,
+	MIPS32R6_INS_MTHC2,
+	MIPS32R6_INS_MTHI,
+	MIPS32R6_INS_MTLO,
 	MIPS32R6_INS_MUL,
-	MIPS32R6_INS_MUH,
-	MIPS32R6_INS_MULU,
-	MIPS32R6_INS_MUHU,
+	MIPS32R6_INS_MULT,
+	MIPS32R6_INS_MULTU,
+	MIPS32R6_INS_NOR,
+	MIPS32R6_INS_OR,
+	MIPS32R6_INS_ORI,
+	MIPS32R6_INS_PREF,
+	MIPS32R6_INS_PREFX,
+	MIPS32R6_INS_RDHWR,
+	MIPS32R6_INS_RDPGPR,
+	MIPS32R6_INS_ROTR,
+	MIPS32R6_INS_ROTRV,
 	MIPS32R6_INS_SB,
+	MIPS32R6_INS_SC,
+	MIPS32R6_INS_SDBBP,
+	MIPS32R6_INS_SDC1,
+	MIPS32R6_INS_SDC2,
+	MIPS32R6_INS_SDXC1,
+	MIPS32R6_INS_SEB,
+	MIPS32R6_INS_SEH,
 	MIPS32R6_INS_SH,
-	MIPS32R6_INS_SW,
 	MIPS32R6_INS_SLL,
 	MIPS32R6_INS_SLLV,
 	MIPS32R6_INS_SLT,
@@ -60,21 +222,54 @@ enum mips32r6_instruction_type {
 	MIPS32R6_INS_SRLV,
 	MIPS32R6_INS_SUB,
 	MIPS32R6_INS_SUBU,
+	MIPS32R6_INS_SUXC1,
+	MIPS32R6_INS_SW,
+	MIPS32R6_INS_SWC1,
+	MIPS32R6_INS_SWC2,
+	MIPS32R6_INS_SWL,
+	MIPS32R6_INS_SWR,
+	MIPS32R6_INS_SWXC1,
+	MIPS32R6_INS_SYNC,
+	MIPS32R6_INS_SYNCI,
 	MIPS32R6_INS_SYSCALL,
-	MIPS32R6_INS_OR,
-	MIPS32R6_INS_ORI,
-	MIPS32R6_INS_NOR,
+	MIPS32R6_INS_TEQ,
+	MIPS32R6_INS_TEQI,
+	MIPS32R6_INS_TGE,
+	MIPS32R6_INS_TGEI,
+	MIPS32R6_INS_TGEIU,
+	MIPS32R6_INS_TGEU,
+	MIPS32R6_INS_TLBP,
+	MIPS32R6_INS_TLBR,
+	MIPS32R6_INS_TLBWI,
+	MIPS32R6_INS_TLBWR,
+	MIPS32R6_INS_TLT,
+	MIPS32R6_INS_TLTI,
+	MIPS32R6_INS_TLTIU,
+	MIPS32R6_INS_TLTU,
+	MIPS32R6_INS_TNE,
+	MIPS32R6_INS_TNEI,
+	MIPS32R6_INS_WAIT,
+	MIPS32R6_INS_WRPGPR,
+	MIPS32R6_INS_WSBH,
 	MIPS32R6_INS_XOR,
 	MIPS32R6_INS_XORI,
 	__MIPS32R6_INS_NULL,
 };
 
+// op code groups
 #define MIPS32R6_OP_SPECIAL    0b000000
+#define MIPS32R6_OP_SPECIAL2   0b011100
+#define MIPS32R6_OP_SPECIAL3   0b011111
+#define MIPS32R6_OP_REGIMM     0b000001
+#define MIPS32R6_OP_COP0       0b010000
+#define MIPS32R6_OP_COP1       0b010001
+#define MIPS32R6_OP_COP2       0b010010
+#define MIPS32R6_OP_COP1X      0b010011
+
+// op codes
 #define MIPS32R6_OP_ADDI       0b001000
 #define MIPS32R6_OP_ADDIU      0b001001
 #define MIPS32R6_OP_ANDI       0b001100
-#define MIPS32R6_OP_REGIMM     0b000001
-#define MIPS32R6_OP_BALC       0b111010
 #define MIPS32R6_OP_BC         0b110010
 #define MIPS32R6_OP_BEQ        0b000100
 #define MIPS32R6_OP_BEQL       0b010100
@@ -84,36 +279,59 @@ enum mips32r6_instruction_type {
 #define MIPS32R6_OP_BLEZL      0b010110
 #define MIPS32R6_OP_BNE        0b000101
 #define MIPS32R6_OP_BNEL       0b010101
+#define MIPS32R6_OP_CACHE      0b101111
 #define MIPS32R6_OP_J          0b000010
 #define MIPS32R6_OP_JAL        0b000011
 #define MIPS32R6_OP_JALX       0b011101
 #define MIPS32R6_OP_LB         0b100000
 #define MIPS32R6_OP_LBU        0b100100
+#define MIPS32R6_OP_LDC1       0b110101
+#define MIPS32R6_OP_LDC2       0b110110
 #define MIPS32R6_OP_LH         0b100001
 #define MIPS32R6_OP_LHU        0b100101
+#define MIPS32R6_OP_LL         0b110000
 #define MIPS32R6_OP_LUI        0b001111
 #define MIPS32R6_OP_LW         0b100011
+#define MIPS32R6_OP_LWC1       0b110001
+#define MIPS32R6_OP_LWC2       0b110010
+#define MIPS32R6_OP_LWL        0b100010
+#define MIPS32R6_OP_LWR        0b100110
+#define MIPS32R6_OP_ORI        0b001101
+#define MIPS32R6_OP_PREF       0b110011
 #define MIPS32R6_OP_SB         0b101000
+#define MIPS32R6_OP_SC         0b111000
+#define MIPS32R6_OP_SDC1       0b111101
+#define MIPS32R6_OP_SDC2       0b111110
 #define MIPS32R6_OP_SH         0b101001
-#define MIPS32R6_OP_SW         0b101011
 #define MIPS32R6_OP_SLTI       0b001010
 #define MIPS32R6_OP_SLTIU      0b001011
-#define MIPS32R6_OP_ORI        0b001101
+#define MIPS32R6_OP_SW         0b101011
+#define MIPS32R6_OP_SWC1       0b111001
+#define MIPS32R6_OP_SWC2       0b111010
+#define MIPS32R6_OP_SWL        0b101010
+#define MIPS32R6_OP_SWR        0b101110
 #define MIPS32R6_OP_XORI       0b001110
 
+// op special
 #define MIPS32R6_FUNCT_ADD     0b100000
 #define MIPS32R6_FUNCT_ADDU    0b100001
 #define MIPS32R6_FUNCT_AND     0b100100
-#define MIPS32R6_FUNCT_SOP32   0b011010
-#define MIPS32R6_FUNCT_SOP33   0b011011
+#define MIPS32R6_FUNCT_BREAK   0b001101
+#define MIPS32R6_FUNCT_DIV     0b000011
+#define MIPS32R6_FUNCT_DIVU    0b011011
 #define MIPS32R6_FUNCT_JALR    0b001001
 #define MIPS32R6_FUNCT_JR      0b001000
 #define MIPS32R6_FUNCT_MFHI    0b010000
 #define MIPS32R6_FUNCT_MFLO    0b010010
+#define MIPS32R6_FUNCT_MOVCL   0b000001
+#define MIPS32R6_FUNCT_MOVN    0b001011
+#define MIPS32R6_FUNCT_MOVZ    0b001010
 #define MIPS32R6_FUNCT_MTHI    0b010001
 #define MIPS32R6_FUNCT_MTLO    0b010011
-#define MIPS32R6_FUNCT_SOP30   0b011000
-#define MIPS32R6_FUNCT_SOP31   0b011001
+#define MIPS32R6_FUNCT_MULT    0b011000
+#define MIPS32R6_FUNCT_MULTU   0b011001
+#define MIPS32R6_FUNCT_NOR     0b100111
+#define MIPS32R6_FUNCT_OR      0b100101
 #define MIPS32R6_FUNCT_SLL     0b000000
 #define MIPS32R6_FUNCT_SLLV    0b000100
 #define MIPS32R6_FUNCT_SLT     0b101010
@@ -124,12 +342,38 @@ enum mips32r6_instruction_type {
 #define MIPS32R6_FUNCT_SRLV    0b000110
 #define MIPS32R6_FUNCT_SUB     0b100010
 #define MIPS32R6_FUNCT_SUBU    0b100011
+#define MIPS32R6_FUNCT_SYNC    0b001111
 #define MIPS32R6_FUNCT_SYSCALL 0b001100
-#define MIPS32R6_FUNCT_OR      0b100101
-#define MIPS32R6_FUNCT_NOR     0b100111
+#define MIPS32R6_FUNCT_TEQ     0b110100
+#define MIPS32R6_FUNCT_TGE     0b110000
+#define MIPS32R6_FUNCT_TGEU    0b110001
+#define MIPS32R6_FUNCT_TLT     0b110010
+#define MIPS32R6_FUNCT_TLTU    0b110011
+#define MIPS32R6_FUNCT_TNE     0b110110
 #define MIPS32R6_FUNCT_XOR     0b100110
 
-#define MIPS32R6_FUNCT_BAL     0b10001
+// op special2
+#define MIPS32R6_FUNCT_CLO     0b100001
+#define MIPS32R6_FUNCT_CLZ     0b100000
+#define MIPS32R6_FUNCT_MADD    0b000000
+#define MIPS32R6_FUNCT_MADDU   0b000001
+#define MIPS32R6_FUNCT_MSUB    0b000100
+#define MIPS32R6_FUNCT_MSUBU   0b000101
+#define MIPS32R6_FUNCT_MUL     0b000010
+#define MIPS32R6_FUNCT_SDBBP   0b111111
+
+// op special 3
+#define MIPS32R6_FUNCT_EXT     0b000000
+#define MIPS32R6_FUNCT_INS     0b000100
+#define MIPS32R6_FUNCT_RDHWR   0b111011
+#define MIPS32R6_FUNCT_BSHFL   0b100000
+
+// op bshfl
+#define MIPS32R6_FUNCT_SEB     0b10000
+#define MIPS32R6_FUNCT_SEH     0b11000
+#define MIPS32R6_FUNCT_WSBH    0b00010
+
+// op regimm
 #define MIPS32R6_FUNCT_BGEZ    0b00001
 #define MIPS32R6_FUNCT_BGEZAL  0b10001
 #define MIPS32R6_FUNCT_BGEZALL 0b10011
@@ -138,18 +382,46 @@ enum mips32r6_instruction_type {
 #define MIPS32R6_FUNCT_BLTZAL  0b10000
 #define MIPS32R6_FUNCT_BLTZALL 0b10010
 #define MIPS32R6_FUNCT_BLTZL   0b00010
+#define MIPS32R6_FUNCT_SYNCI   0b11111
+#define MIPS32R6_FUNCT_TEQI    0b01100
+#define MIPS32R6_FUNCT_TGEI    0b01000
+#define MIPS32R6_FUNCT_TGEIU   0b01001
+#define MIPS32R6_FUNCT_TLTI    0b01010
+#define MIPS32R6_FUNCT_TLTIU   0b01011
+#define MIPS32R6_FUNCT_TNEI    0b01110
+
+// op cop cfunct
+#define MIPS32R6_FUNCT_BC      0b01000
+#define MIPS32R6_FUNCT_CF      0b00010
+#define MIPS32R6_FUNCT_CT      0b00110
+#define MIPS32R6_FUNCT_MF      0b00000
+#define MIPS32R6_FUNCT_MFH     0b00011
+#define MIPS32R6_FUNCT_MT      0b00100
+#define MIPS32R6_FUNCT_MTH     0b00111
+#define MIPS32R6_FUNCT_MFMC0   0b01011
+#define MIPS32R6_FUNCT_RDPGPR  0b01010
+#define MIPS32R6_FUNCT_WRPGPR  0b01110
+
+// op cop funct
+#define MIPS32R6_FUNCT_DERET   0b011111
+#define MIPS32R6_FUNCT_ERET    0b011000
+#define MIPS32R6_FUNCT_TLBP    0b001000
+#define MIPS32R6_FUNCT_TLBR    0b000001
+#define MIPS32R6_FUNCT_TLBWI   0b000010
+#define MIPS32R6_FUNCT_TLBWR   0b000110
 
-#define MIPS32R6_SOP30_MUL     0b00010
-#define MIPS32R6_SOP30_MUH     0b00011
-#define MIPS32R6_SOP31_MULU    0b00010
-#define MIPS32R6_SOP31_MUHU    0b00011
-#define MIPS32R6_SOP32_DIV     0b00010
-#define MIPS32R6_SOP32_MOD     0b00011
-#define MIPS32R6_SOP33_DIVU    0b00010
-#define MIPS32R6_SOP33_MODU    0b00011
+// op cop1x
+#define MIPS32R6_FUNCT_LDXC1   0b000001
+#define MIPS32R6_FUNCT_LUXC1   0b000101
+#define MIPS32R6_FUNCT_LWXC1   0b000000
+#define MIPS32R6_FUNCT_PREFX   0b001111
+#define MIPS32R6_FUNCT_SDXC1   0b001001
+#define MIPS32R6_FUNCT_SUXC1   0b001101
+#define MIPS32R6_FUNCT_SWXC1   0b001000
+#define MIPS32R6_FUNCT_WAIT    0b100000
 
 #define __MIPS32R6_INS_LEN	(__MIPS32R6_INS_NULL)
-#define __MIPS32R6_PSEUDO_LEN	(4)
+#define __MIPS32R6_PSEUDO_LEN	(38)
 #define __MIPS32R6_GRAMMER_LEN	(__MIPS32R6_INS_LEN + __MIPS32R6_PSEUDO_LEN)
 
 extern struct mips32_grammer mips32r6_grammers[__MIPS32R6_GRAMMER_LEN];