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https://git.stationery.faith/corn/corn.git
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pic done
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parent
0d2f0d2491
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GPG key ID:
744AB800E383AE52
5 changed files with 149 additions and 46 deletions
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@ -1,6 +1,11 @@
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extern idt_exception_handler
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global isr_stub_table
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extern idt_pic_timer
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extern idt_pic_keyboard
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extern idt_pic_mouse
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extern idt_pic_eoi
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%macro PUSHALL 0
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push rbx
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push rcx
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@ -62,6 +67,49 @@ isr_stub_%+%1:
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iretq
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%endmacro
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%macro PICGeneric 1
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isr_stub_%+%1:
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PUSHALL
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cld
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mov rdi, %1
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call idt_pic_eoi
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POPALL
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iretq
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%endmacro
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%macro PICTimer 1
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isr_stub_%+%1:
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PUSHALL
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cld
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call idt_pic_timer
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mov rdi, %1
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call idt_pic_eoi
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POPALL
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iretq
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%endmacro
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%macro PICKeyboard 1
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isr_stub_%+%1:
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PUSHALL
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cld
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call idt_pic_keyboard
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mov rdi, %1
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call idt_pic_eoi
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POPALL
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iretq
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%endmacro
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%macro PICMouse 1
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isr_stub_%+%1:
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PUSHALL
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cld
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call idt_pic_mouse
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mov rdi, %1
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call idt_pic_eoi
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POPALL
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iretq
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%endmacro
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; do nothing
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; args: interrupt number
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%macro ISRIgnore 1
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@ -107,10 +155,26 @@ ISRExceptionCode 29
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ISRExceptionCode 30
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ISRException 31
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%assign i 32
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PICTimer 32 ; 0
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PICKeyboard 33 ; 1
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PICGeneric 34 ; 2
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PICGeneric 35 ; 3
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PICGeneric 36 ; 4
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PICGeneric 37 ; 5
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PICGeneric 38 ; 6
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PICGeneric 39 ; 7
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PICGeneric 40 ; 8
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PICGeneric 41 ; 9
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PICGeneric 42 ; 10
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PICGeneric 43 ; 11
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PICMouse 44 ; 12
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PICGeneric 45 ; 13
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PICGeneric 46 ; 14
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PICGeneric 47 ; 15
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; ignore other interrupts
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%rep 0x100 - i
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%assign i 48
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%rep 256 - i
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ISRIgnore i
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%assign i i+1
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%endrep
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@ -5,6 +5,7 @@
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#include <serial.h>
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#include "idt.h"
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#include "pic.h"
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#define IDT_SIZE 256
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@ -106,6 +107,28 @@ char *EXCEPTIONS[] = {
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"Exception 0x1F Reserved",
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};
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void idt_pic_eoi(uint8_t exception) {
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pic_eoi(exception - PIC_REMAP_OFFSET);
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}
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static size_t timer = 0;
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void idt_pic_timer(void) {
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timer += 1;
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char buf[20];
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ltoa(timer, buf, 10);
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serial_out_str(buf);
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serial_out_str("\n");
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}
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void idt_pic_keyboard(void) {
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serial_out_str("ps2 kbd");
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}
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void idt_pic_mouse(void) {
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serial_out_str("ps2 mouse");
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}
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void idt_exception_handler(uint64_t exception, uint64_t code) {
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// TODO don't just panic
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char buf[80];
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@ -1,78 +1,89 @@
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#include "bindings.h"
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#include "pic.h"
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#define PIC1_COMMAND_PORT 0x20
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#define PIC1_DATA_PORT 0x21
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#define PIC2_COMMAND_PORT 0xA0
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#define PIC2_DATA_PORT 0xA1
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#define PIC1 0x20 /* IO base address for master PIC */
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#define PIC2 0xA0 /* IO base address for slave PIC */
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#define PIC1_COMMAND PIC1
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#define PIC1_DATA (PIC1+1)
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#define PIC2_COMMAND PIC2
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#define PIC2_DATA (PIC2+1)
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#define PIC_EOI 0x20 /* End-of-interrupt command code */
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#define ICW1_ICW4 0x01 /* Indicates that ICW4 will be present */
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#define ICW1_SINGLE 0x02 /* Single (cascade) mode */
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#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */
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#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
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#define ICW1_INIT 0x10 /* Initialization - required! */
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#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
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#define ICW4_AUTO 0x02 /* Auto (normal) EOI */
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#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
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#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
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#define ICW4_SFNM 0x10 /* Special fully nested (not) */
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void pic_remap(void) {
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char a1 = inb(PIC1_DATA_PORT);
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char a2 = inb(PIC2_DATA_PORT);
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// control word 1
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// 0x11: initialize, enable ICW4
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outb(PIC1_COMMAND_PORT, 0x11);
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uint8_t a1, a2;
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a1 = inb(PIC1_DATA); // save masks
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a2 = inb(PIC2_DATA);
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outb(PIC1_COMMAND, ICW1_INIT | ICW1_ICW4); // starts the initialization sequence (in cascade mode)
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io_wait();
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outb(PIC2_COMMAND_PORT, 0x11);
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outb(PIC2_COMMAND, ICW1_INIT | ICW1_ICW4);
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io_wait();
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// control word 2
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// interrupt offset
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outb(PIC1_DATA_PORT, PIC_REMAP_OFFSET);
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outb(PIC1_DATA, PIC_REMAP_OFFSET); // ICW2: Master PIC vector offset
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io_wait();
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outb(PIC2_DATA_PORT, PIC_REMAP_OFFSET + 8);
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outb(PIC2_DATA, PIC_REMAP_OFFSET + 8); // ICW2: Slave PIC vector offset
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io_wait();
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// control word 3
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// primary pic: set which pin secondary is connected to
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// (pin 2)
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outb(PIC1_DATA_PORT, 0x04);
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outb(PIC1_DATA, 4); // ICW3: tell Master PIC that there is a slave PIC at IRQ2 (0000 0100)
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io_wait();
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outb(PIC2_DATA_PORT, 2);
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outb(PIC2_DATA, 2); // ICW3: tell Slave PIC its cascade identity (0000 0010)
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io_wait();
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// control word 3
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// 0x01: enable 8086 mode
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outb(PIC1_DATA_PORT, 0x01);
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outb(PIC1_DATA, ICW4_8086); // ICW4: have the PICs use 8086 mode (and not 8080 mode)
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io_wait();
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outb(PIC2_DATA_PORT, 0x01);
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outb(PIC2_DATA, ICW4_8086);
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io_wait();
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// clear data registers
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outb(PIC1_DATA_PORT, a1);
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outb(PIC2_DATA_PORT, a2);
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outb(PIC1_DATA, a1); // restore saved masks.
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outb(PIC2_DATA, a2);
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}
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void pic_mask(int irq) {
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uint8_t port;
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uint16_t port;
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uint8_t mask;
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if(irq < 8) {
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port = PIC1_DATA_PORT;
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port = PIC1_DATA;
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} else {
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port = PIC2_DATA;
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irq -= 8;
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port = PIC2_DATA_PORT;
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}
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uint8_t mask = inb(port);
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outb(port, mask | (1 << irq));
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mask = inb(port) | (1 << irq);
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outb(port, mask);
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}
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void pic_unmask(int irq) {
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uint8_t port;
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uint16_t port;
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uint8_t mask;
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if(irq < 8) {
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port = PIC1_DATA_PORT;
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port = PIC1_DATA;
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} else {
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irq -= 8;
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port = PIC2_DATA_PORT;
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port = PIC2_DATA;
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}
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uint8_t mask = inb(port);
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outb(port, mask & ~(1 << irq));
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mask = inb(port) & ~(1 << irq);
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outb(port, mask);
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}
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void pic_disable(void) {
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outb(PIC1_DATA_PORT, 0xff);
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io_wait();
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outb(PIC2_DATA_PORT, 0xff);
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io_wait();
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outb(PIC1_DATA, 0xff);
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outb(PIC2_DATA, 0xff);
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}
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void pic_eoi(int irq) {
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if(irq >= 8) {
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outb(PIC2_COMMAND_PORT, 0x20);
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outb(PIC2_COMMAND, PIC_EOI);
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}
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outb(PIC1_COMMAND_PORT, 0x20);
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outb(PIC1_COMMAND, PIC_EOI);
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}
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@ -12,12 +12,13 @@
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static struct boot_info boot_info;
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void* amd64_shim(void *mboot_data_ptr) {
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serial_init();
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paging_init();
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idt_init();
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pic_remap();
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idt_init();
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kmap_page(mboot_data_ptr, mboot_data_ptr, F_WRITEABLE);
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//kmap_page(mboot_data_ptr, mboot_data_ptr, F_WRITEABLE);
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struct mboot_info mboot_info;
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mboot_info = mboot_load_info(mboot_data_ptr);
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@ -13,4 +13,8 @@ void kmain(struct boot_info *info) {
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itoa(*(long*)info, buf, 16);
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//fb_init(1024, 768);
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serial_out_str(buf);
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while (1) {
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// loop so we dont halt
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// this allows interrupts to fire
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}
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}
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