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#include <stdint.h>
#include <cpuid.h>
#define PG_PRESENT 0x0000'0000'0000'0001
#define PG_READ_WRITE 0x0000'0000'0000'0002
#define PG_USER_SUPERVISE 0x0000'0000'0000'0004
#define PG_WRITE_THROUGH 0x0000'0000'0000'0008
#define PG_CACHE_DISABLE 0x0000'0000'0000'0010
#define PG_ACCESSED 0x0000'0000'0000'0020
#define PG_EXECUTE_DISABLE 0x8000'0000'0000'0000
#define F_PRESENT 0b1
#define F_WRITEABLE 0b10
#define F_UNPRIVILEGED 0b100
#define F_WRITETHROUGH 0b1000
#define F_CACHEDISABLE 0b10000
#define F_ACCESSED 0b100000
#define F_DIRTY 0b1000000
#define F_MEGABYTE 0b10000000
#define F_GLOBAL 0b100000000
// PAGE MAP LEVEL 4 ENTRY
struct pml4e {
uint64_t flags : 6;
uint64_t : 6;
uint64_t address : 40;
uint64_t : 11;
uint64_t execute_disable : 1;
};
// PAGE DIRECTORY POINTER TABLE ENTRY
struct pdpte {
uint64_t flags : 6;
uint64_t : 1;
uint64_t page_size : 1;
uint64_t : 4;
uint64_t address : 40;
uint64_t : 11;
uint64_t execute_disable : 1;
};
// PAGE DIRECTORY ENTRY
struct pde {
uint64_t flags : 6;
uint64_t : 1;
uint64_t page_size : 1;
uint64_t : 4;
uint64_t address : 40;
uint64_t : 11;
uint64_t execute_disable : 1;
};
// PAGE TABLE ENTRY
struct pte {
uint64_t flags : 9;
uint64_t : 3;
uint64_t address : 40;
uint64_t : 7;
uint64_t protection_key : 4;
uint64_t execute_disable : 1;
};
static int get_maxphysaddr() {
uint32_t eax, ebx, ecx, edx;
__cpuid(0x80000008, eax, ebx, ecx, edx);
return eax & 0xFF;
}
// entry point for amd64
void* amd64_shim(void *boot_info) {
struct pml4e *pml4 = (struct pml4e *)0x1000;
struct pdpte *pdpt = (struct pdpte *)0x2000;
struct pde *pd = (struct pd *)0x3000;
struct pte *pt = (struct pt *)0x4000;
pd[1].flags = F_PRESENT | F_WRITEABLE;
pd[1].address = ((uint64_t)pt) >> 12;
__asm("invlpg 0x200000");
}
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