blob: e28291b308e28ce7e68af498198e87e14b12ae34 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
|
#include <stdint.h>
// PAGE MAP LEVEL 4 ENTRY
struct pml4 {
uint64_t present : 1;
uint64_t rw : 1;
uint64_t user_supervisor : 1;
uint64_t write_through : 1;
uint64_t cache_disable : 1;
uint64_t accessed : 1;
uint64_t _reserved : 6;
uint64_t address : 40;
uint64_t _reserved_2 : 11;
uint64_t execute_disable : 1;
};
// PAGE DIRECTORY POINTER TABLE ENTRY
struct pdpte {
uint64_t present : 1;
uint64_t rw : 1;
uint64_t user_supervisor : 1;
uint64_t write_through : 1;
uint64_t cache_disable : 1;
uint64_t accessed : 1;
uint64_t _reserved : 1;
uint64_t page_size : 1;
uint64_t _reserved_2 : 2;
uint64_t address : 40;
uint64_t _reserved_3 : 11;
uint64_t execute_disable : 1;
};
// PAGE DIRECTORY ENTRY
struct pde {
uint64_t present : 1;
uint64_t rw : 1;
uint64_t user_supervisor : 1;
uint64_t write_through : 1;
uint64_t cache_disable : 1;
uint64_t accessed : 1;
uint64_t _reserved : 1;
uint64_t page_size : 1;
uint64_t _reserved_2 : 2;
uint64_t address : 40;
uint64_t _reserved_3 : 11;
uint64_t execute_disable : 1;
};
// PAGE TABLE ENTRY
struct pte {
uint64_t present : 1;
uint64_t rw : 1;
uint64_t user_supervisor : 1;
uint64_t write_through : 1;
uint64_t cache_disable : 1;
uint64_t accessed : 1;
uint64_t dirty : 1;
uint64_t mem_type : 1;
uint64_t global : 1;
uint64_t _reserved : 3;
uint64_t address : 40;
uint64_t _reserved_2 : 7;
uint64_t protection_key : 4;
uint64_t execute_disable : 1;
};
// entry point for amd64
void amd64_shim(void *boot_info) {
}
|
