diff options
Diffstat (limited to 'src/arch/amd64/pic.c')
-rw-r--r-- | src/arch/amd64/pic.c | 95 |
1 files changed, 53 insertions, 42 deletions
diff --git a/src/arch/amd64/pic.c b/src/arch/amd64/pic.c index ebf6b40..b4907d0 100644 --- a/src/arch/amd64/pic.c +++ b/src/arch/amd64/pic.c @@ -1,78 +1,89 @@ #include "bindings.h" #include "pic.h" -#define PIC1_COMMAND_PORT 0x20 -#define PIC1_DATA_PORT 0x21 -#define PIC2_COMMAND_PORT 0xA0 -#define PIC2_DATA_PORT 0xA1 +#define PIC1 0x20 /* IO base address for master PIC */ +#define PIC2 0xA0 /* IO base address for slave PIC */ +#define PIC1_COMMAND PIC1 +#define PIC1_DATA (PIC1+1) +#define PIC2_COMMAND PIC2 +#define PIC2_DATA (PIC2+1) + +#define PIC_EOI 0x20 /* End-of-interrupt command code */ + +#define ICW1_ICW4 0x01 /* Indicates that ICW4 will be present */ +#define ICW1_SINGLE 0x02 /* Single (cascade) mode */ +#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */ +#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */ +#define ICW1_INIT 0x10 /* Initialization - required! */ + +#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */ +#define ICW4_AUTO 0x02 /* Auto (normal) EOI */ +#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */ +#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */ +#define ICW4_SFNM 0x10 /* Special fully nested (not) */ void pic_remap(void) { - char a1 = inb(PIC1_DATA_PORT); - char a2 = inb(PIC2_DATA_PORT); - // control word 1 - // 0x11: initialize, enable ICW4 - outb(PIC1_COMMAND_PORT, 0x11); + uint8_t a1, a2; + + a1 = inb(PIC1_DATA); // save masks + a2 = inb(PIC2_DATA); + + outb(PIC1_COMMAND, ICW1_INIT | ICW1_ICW4); // starts the initialization sequence (in cascade mode) io_wait(); - outb(PIC2_COMMAND_PORT, 0x11); + outb(PIC2_COMMAND, ICW1_INIT | ICW1_ICW4); io_wait(); - // control word 2 - // interrupt offset - outb(PIC1_DATA_PORT, PIC_REMAP_OFFSET); + outb(PIC1_DATA, PIC_REMAP_OFFSET); // ICW2: Master PIC vector offset io_wait(); - outb(PIC2_DATA_PORT, PIC_REMAP_OFFSET + 8); + outb(PIC2_DATA, PIC_REMAP_OFFSET + 8); // ICW2: Slave PIC vector offset io_wait(); - // control word 3 - // primary pic: set which pin secondary is connected to - // (pin 2) - outb(PIC1_DATA_PORT, 0x04); + outb(PIC1_DATA, 4); // ICW3: tell Master PIC that there is a slave PIC at IRQ2 (0000 0100) io_wait(); - outb(PIC2_DATA_PORT, 2); + outb(PIC2_DATA, 2); // ICW3: tell Slave PIC its cascade identity (0000 0010) io_wait(); - // control word 3 - // 0x01: enable 8086 mode - outb(PIC1_DATA_PORT, 0x01); + + outb(PIC1_DATA, ICW4_8086); // ICW4: have the PICs use 8086 mode (and not 8080 mode) io_wait(); - outb(PIC2_DATA_PORT, 0x01); + outb(PIC2_DATA, ICW4_8086); io_wait(); - // clear data registers - outb(PIC1_DATA_PORT, a1); - outb(PIC2_DATA_PORT, a2); + + outb(PIC1_DATA, a1); // restore saved masks. + outb(PIC2_DATA, a2); } void pic_mask(int irq) { - uint8_t port; + uint16_t port; + uint8_t mask; if(irq < 8) { - port = PIC1_DATA_PORT; + port = PIC1_DATA; } else { + port = PIC2_DATA; irq -= 8; - port = PIC2_DATA_PORT; } - uint8_t mask = inb(port); - outb(port, mask | (1 << irq)); + mask = inb(port) | (1 << irq); + outb(port, mask); } void pic_unmask(int irq) { - uint8_t port; + uint16_t port; + uint8_t mask; if(irq < 8) { - port = PIC1_DATA_PORT; + port = PIC1_DATA; } else { irq -= 8; - port = PIC2_DATA_PORT; + port = PIC2_DATA; } - uint8_t mask = inb(port); - outb(port, mask & ~(1 << irq)); + mask = inb(port) & ~(1 << irq); + outb(port, mask); } void pic_disable(void) { - outb(PIC1_DATA_PORT, 0xff); - io_wait(); - outb(PIC2_DATA_PORT, 0xff); - io_wait(); + outb(PIC1_DATA, 0xff); + outb(PIC2_DATA, 0xff); } void pic_eoi(int irq) { if(irq >= 8) { - outb(PIC2_COMMAND_PORT, 0x20); + outb(PIC2_COMMAND, PIC_EOI); } - outb(PIC1_COMMAND_PORT, 0x20); + outb(PIC1_COMMAND, PIC_EOI); } |