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-rw-r--r--include/x86/arch.h3
-rw-r--r--include/x86/bios.h2
-rw-r--r--include/x86/ops.h21
-rw-r--r--include/x86/pic.h3
-rw-r--r--include/x86/pit.h2
-rw-r--r--include/x86/uart.h1
6 files changed, 1 insertions, 31 deletions
diff --git a/include/x86/arch.h b/include/x86/arch.h
index a0a0b45..df0b2e2 100644
--- a/include/x86/arch.h
+++ b/include/x86/arch.h
@@ -41,7 +41,6 @@
** See IA-32 Intel Architecture SW Dev. Manual, Volume 3: System
** Programming Guide, page 2-8.
*/
-
/*
** EFLAGS
*/
@@ -142,7 +141,6 @@
** 4: base address 23:16
** 7: base address 31:24
*/
-
/*
** Byte 5: access control bits
** 7: present
@@ -261,7 +259,6 @@
/*
** Interrupt vectors
*/
-
// predefined by the architecture
#define VEC_DIVIDE_ERROR 0x00
#define VEC_DEBUG_EXCEPTION 0x01
diff --git a/include/x86/bios.h b/include/x86/bios.h
index cf9f8ec..f1debbf 100644
--- a/include/x86/bios.h
+++ b/include/x86/bios.h
@@ -12,13 +12,11 @@
/*
** BIOS-related memory addresses
*/
-
#define BIOS_BDA 0x0400
/*
** Selected BIOS interrupt numbers
*/
-
#define BIOS_TIMER 0x08
#define BIOS_KBD 0x09
#define BIOS_VIDEO 0x10
diff --git a/include/x86/ops.h b/include/x86/ops.h
index 97ecdd6..81167a1 100644
--- a/include/x86/ops.h
+++ b/include/x86/ops.h
@@ -54,7 +54,6 @@ static inline void movsb(void *dst, const void *src, uint32_t len) OPSINLINED
:
: "memory");
}
-
static inline void movsw(void *dst, const void *src, uint32_t len) OPSINLINED
{
__asm__ __volatile__("cld; rep movsw"
@@ -62,7 +61,6 @@ static inline void movsw(void *dst, const void *src, uint32_t len) OPSINLINED
:
: "memory");
}
-
static inline void movsl(void *dst, const void *src, uint32_t len) OPSINLINED
{
__asm__ __volatile__("cld; rep movsl"
@@ -70,7 +68,6 @@ static inline void movsl(void *dst, const void *src, uint32_t len) OPSINLINED
:
: "memory");
}
-
static inline void movsq(void *dst, const void *src, uint32_t len) OPSINLINED
{
__asm__ __volatile__("cld; rep movsq"
@@ -97,7 +94,6 @@ static inline void stosb(void *dst, uint8_t val, uint32_t len) OPSINLINED
: "0"(dst), "1"(len), "a"(val)
: "memory", "cc");
}
-
static inline void stosw(void *dst, uint16_t val, uint32_t len) OPSINLINED
{
__asm__ __volatile__("cld; rep stos2"
@@ -105,7 +101,6 @@ static inline void stosw(void *dst, uint16_t val, uint32_t len) OPSINLINED
: "0"(dst), "1"(len), "a"(val)
: "memory", "cc");
}
-
static inline void stosl(void *dst, uint32_t val, uint32_t len) OPSINLINED
{
__asm__ __volatile__("cld; rep stosl"
@@ -134,42 +129,36 @@ static inline uint32_t r_cr0(void) OPSINLINED
__asm__ __volatile__("movl %%cr0,%0" : "=r"(val));
return val;
}
-
static inline uint32_t r_cr2(void) OPSINLINED
{
uint32_t val;
__asm__ __volatile__("movl %%cr2,%0" : "=r"(val));
return val;
}
-
static inline uint32_t r_cr3(void) OPSINLINED
{
uint32_t val;
__asm__ __volatile__("movl %%cr3,%0" : "=r"(val));
return val;
}
-
static inline uint32_t r_cr4(void) OPSINLINED
{
uint32_t val;
__asm__ __volatile__("movl %%cr4,%0" : "=r"(val));
return val;
}
-
static inline uint32_t r_eflags(void) OPSINLINED
{
uint32_t val;
__asm__ __volatile__("pushfl; popl %0" : "=r"(val));
return val;
}
-
static inline uint32_t r_ebp(void) OPSINLINED
{
uint32_t val;
__asm__ __volatile__("movl %%ebp,%0" : "=r"(val));
return val;
}
-
static inline uint32_t r_esp(void) OPSINLINED
{
uint32_t val;
@@ -188,22 +177,18 @@ static inline void w_cr0(uint32_t val) OPSINLINED
{
__asm__ __volatile__("movl %0,%%cr0" : : "r"(val));
}
-
static inline void w_cr2(uint32_t val) OPSINLINED
{
__asm__ __volatile__("movl %0,%%cr2" : : "r"(val));
}
-
static inline void w_cr3(uint32_t val) OPSINLINED
{
__asm__ __volatile__("movl %0,%%cr3" : : "r"(val));
}
-
static inline void w_cr4(uint32_t val) OPSINLINED
{
__asm__ __volatile__("movl %0,%%cr4" : : "r"(val));
}
-
static inline void w_eflags(uint32_t eflags) OPSINLINED
{
__asm__ __volatile__("pushl %0; popfl" : : "r"(eflags));
@@ -222,7 +207,6 @@ static inline void w_gdt(void *addr) OPSINLINED
{
__asm__ __volatile__("lgdt (%0)" : : "r"(addr));
}
-
static inline void w_idt(void *addr) OPSINLINED
{
__asm__ __volatile__("lidt (%0)" : : "r"(addr));
@@ -246,7 +230,6 @@ static inline void cpuid(uint32_t op, uint32_t *ap, uint32_t *bp, uint32_t *cp,
__asm__ __volatile__("cpuid"
: "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
: "a"(op));
-
if (ap)
*ap = eax;
if (bp)
@@ -308,14 +291,12 @@ static inline uint8_t inb(int port) OPSINLINED
__asm__ __volatile__("inb %w1,%0" : "=a"(data) : "d"(port));
return data;
}
-
static inline uint16_t inw(int port) OPSINLINED
{
uint16_t data;
__asm__ __volatile__("inw %w1,%0" : "=a"(data) : "d"(port));
return data;
}
-
static inline uint32_t inl(int port) OPSINLINED
{
uint32_t data;
@@ -339,12 +320,10 @@ static inline void outb(int port, uint8_t data) OPSINLINED
{
__asm__ __volatile__("outb %0,%w1" : : "a"(data), "d"(port));
}
-
static inline void outw(int port, uint16_t data) OPSINLINED
{
__asm__ __volatile__("outw %0,%w1" : : "a"(data), "d"(port));
}
-
static inline void outl(int port, uint32_t data) OPSINLINED
{
__asm__ __volatile__("outl %0,%w1" : : "a"(data), "d"(port));
diff --git a/include/x86/pic.h b/include/x86/pic.h
index 797799a..ae3fe6c 100644
--- a/include/x86/pic.h
+++ b/include/x86/pic.h
@@ -16,7 +16,6 @@
** Our expected configuration is two PICs, with the secondary connected
** through the IRQ2 pin of the primary.
*/
-
/*
** Port addresses for the command port and interrupt mask register port
** for both the primary and secondary PICs.
@@ -42,7 +41,6 @@
** PIC2_* defines are intended for the secondary PIC
** PIC_* defines are sent to both PICs
*/
-
/*
** ICW1: initialization, send to command port
*/
@@ -79,7 +77,6 @@
**
** After the init sequence, can send these
*/
-
/*
** OCW1: interrupt mask; send to data port
*/
diff --git a/include/x86/pit.h b/include/x86/pit.h
index 854b76a..0c54539 100644
--- a/include/x86/pit.h
+++ b/include/x86/pit.h
@@ -25,7 +25,6 @@
** M - mode
** BCD - binary or BCD counter
*/
-
/* Frequency settings */
#define PIT_DEFAULT_TICKS_PER_SECOND 18 // actually 18.2065Hz
#define PIT_DEFAULT_MS_PER_TICK (1000 / PIT_DEFAULT_TICKS_PER_SECOND)
@@ -68,6 +67,7 @@
#define PIT_2_RATE 0x06 // square-wave, for USART
/* Timer read-back */
+
#define PIT_READBACK 0xc0 // perform a read-back
#define PIT_RB_NOT_COUNT 0x20 // don't latch the count
#define PIT_RB_NOT_STATUS 0x10 // don't latch the status
diff --git a/include/x86/uart.h b/include/x86/uart.h
index 3ec2b8f..293b7b7 100644
--- a/include/x86/uart.h
+++ b/include/x86/uart.h
@@ -66,7 +66,6 @@
** accessed (0 selects Line Control, 1 selects Divisor Latch), with the
** remaining bits selecting fields within the indicated register.
*/
-
/*
** Receiver Data Register (read-only)
*/
generated by cgit v1.2.3-freya (git 2.51.0) at 2025-09-22 19:19:11 +0000