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| author | Freya Murphy <freya@freyacat.org> | 2024-10-09 12:08:58 -0400 |
|---|---|---|
| committer | Freya Murphy <freya@freyacat.org> | 2024-10-09 12:08:58 -0400 |
| commit | 720b95b5d993caacae420b24dcf8a39a97b31871 (patch) | |
| tree | 39e94ad23c57d343733025b4e914cc762fb1a5f1 /include/mips.h | |
| parent | add pseudo instructions test (diff) | |
| download | mips-720b95b5d993caacae420b24dcf8a39a97b31871.tar.gz mips-720b95b5d993caacae420b24dcf8a39a97b31871.tar.bz2 mips-720b95b5d993caacae420b24dcf8a39a97b31871.zip | |
add mips1 and mips32r2 isa definitions
Diffstat (limited to '')
| -rw-r--r-- | include/mips.h (renamed from include/mips32.h) | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/include/mips32.h b/include/mips.h index e2b86b7..8155eb7 100644 --- a/include/mips32.h +++ b/include/mips.h @@ -43,6 +43,42 @@ enum mips32_register { MIPS32_REG_RA = 31, }; +/* all mips fp registers $f0-$f31 */ +enum mips32_fp_register { + MIPS32_REG_F0 = 0, + MIPS32_REG_F1 = 1, + MIPS32_REG_F2 = 2, + MIPS32_REG_F3 = 3, + MIPS32_REG_F4 = 4, + MIPS32_REG_F5 = 5, + MIPS32_REG_F6 = 6, + MIPS32_REG_F7 = 7, + MIPS32_REG_F8 = 8, + MIPS32_REG_F9 = 9, + MIPS32_REG_F10 = 10, + MIPS32_REG_F11 = 11, + MIPS32_REG_F12 = 12, + MIPS32_REG_F13 = 13, + MIPS32_REG_F14 = 14, + MIPS32_REG_F15 = 15, + MIPS32_REG_F16 = 16, + MIPS32_REG_F17 = 17, + MIPS32_REG_F18 = 18, + MIPS32_REG_F19 = 19, + MIPS32_REG_F20 = 20, + MIPS32_REG_F21 = 21, + MIPS32_REG_F22 = 22, + MIPS32_REG_F23 = 23, + MIPS32_REG_F24 = 24, + MIPS32_REG_F25 = 25, + MIPS32_REG_F26 = 26, + MIPS32_REG_F27 = 27, + MIPS32_REG_F28 = 28, + MIPS32_REG_F29 = 29, + MIPS32_REG_F30 = 30, + MIPS32_REG_F31 = 31, +}; + /* mips instruction */ union mips32_instruction { /* raw ins */ @@ -77,6 +113,48 @@ union mips32_instruction { uint32_t bfunct : 5; uint32_t : 11; }; + /* coprocessor */ + struct { + uint32_t : 21; + uint32_t cfunct : 5; + uint32_t : 6; + }; + /* flags */ + struct { + // 6 bit + uint32_t : 5; + uint32_t sc : 1; // interrupt + // 5 bit + uint32_t rv : 1; // rotate variable + uint32_t : 3; + uint32_t hb : 1; // hazard barrier + // 5 bit + uint32_t : 5; + // 5 bit + uint32_t tf : 1; // true false + uint32_t nd : 1; // + uint32_t cc : 3; // code + // 5 bit + uint32_t r : 1; // rotate + uint32_t : 3; + uint32_t c0 : 1; // cop0 + // 6 bit + uint32_t : 6; + }; + /* break code */ + struct { + uint32_t : 6; + uint32_t code : 20; + uint32_t : 6; + }; + /* floating point */ + struct { + uint32_t : 6; + uint32_t fd : 5; + uint32_t fs : 5; + uint32_t ft : 5; + uint32_t : 11; + }; } __attribute__((packed)); /// grammer syntax: |