373 lines
7.6 KiB
C
373 lines
7.6 KiB
C
#include <mips.h>
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#include <melf.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <unistd.h>
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#include "sim.h"
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#define I16(n) ((int32_t)(uint16_t)(n))
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static void sim_ins_special_sop30(struct simulator *sim,
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union mips_instruction_data ins)
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{
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switch (ins.shamt) {
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case MIPS_SOP30_MUL:
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sim->reg[ins.rd] = ((int64_t)sim->reg[ins.rs] /
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(int64_t)sim->reg[ins.rt]) >> 0;
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break;
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case MIPS_SOP30_MUH:
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sim->reg[ins.rd] = ((int64_t)sim->reg[ins.rs] /
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(int64_t)sim->reg[ins.rt]) >> 32;
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break;
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default:
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sim_dump(sim, "unknown sop30 funct (0b%06b)", ins.shamt);
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}
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}
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static void sim_ins_special_sop31(struct simulator *sim,
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union mips_instruction_data ins)
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{
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switch (ins.shamt) {
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case MIPS_SOP31_MULU:
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sim->reg[ins.rd] = ((uint64_t)sim->reg[ins.rs] /
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(uint64_t)sim->reg[ins.rt]) >> 0;
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break;
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case MIPS_SOP31_MUHU:
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sim->reg[ins.rd] = ((uint64_t)sim->reg[ins.rs] /
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(uint64_t)sim->reg[ins.rt]) >> 32;
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break;
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default:
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sim_dump(sim, "unknown sop31 funct (0b%06b)", ins.shamt);
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}
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}
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static void sim_ins_special_sop32(struct simulator *sim,
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union mips_instruction_data ins)
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{
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switch (ins.shamt) {
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case MIPS_SOP32_DIV:
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sim->reg[ins.rd] = (int32_t)sim->reg[ins.rs] /
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(int32_t)sim->reg[ins.rt];
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break;
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case MIPS_SOP32_MOD:
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sim->reg[ins.rd] = (int32_t)sim->reg[ins.rs] %
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(int32_t)sim->reg[ins.rt];
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break;
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default:
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sim_dump(sim, "unknown sop32 funct (0b%06b)", ins.shamt);
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}
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}
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static void sim_ins_special_sop33(struct simulator *sim,
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union mips_instruction_data ins)
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{
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switch (ins.shamt) {
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case MIPS_SOP33_DIVU:
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sim->reg[ins.rd] = sim->reg[ins.rs] / sim->reg[ins.rt];
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break;
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case MIPS_SOP33_MODU:
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sim->reg[ins.rd] = sim->reg[ins.rs] % sim->reg[ins.rt];
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break;
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default:
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sim_dump(sim, "unknown sop33 funct (0b%06b)", ins.shamt);
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}
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}
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static void sim_ins_special(struct simulator *sim,
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union mips_instruction_data ins)
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{
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switch (ins.funct) {
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case MIPS_FUNCT_ADD:
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sim->reg[ins.rd] = (int32_t)sim->reg[ins.rs] +
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(int32_t)sim->reg[ins.rt];
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break;
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case MIPS_FUNCT_ADDU:
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sim->reg[ins.rd] = sim->reg[ins.rs] + sim->reg[ins.rt];
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break;
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case MIPS_FUNCT_AND:
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sim->reg[ins.rd] = sim->reg[ins.rs] & sim->reg[ins.rt];
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break;
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case MIPS_FUNCT_SOP30:
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sim_ins_special_sop30(sim, ins);
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break;
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case MIPS_FUNCT_SOP31:
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sim_ins_special_sop31(sim, ins);
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break;
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case MIPS_FUNCT_SOP32:
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sim_ins_special_sop32(sim, ins);
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break;
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case MIPS_FUNCT_SOP33:
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sim_ins_special_sop33(sim, ins);
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break;
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case MIPS_FUNCT_JALR:
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sim->reg[MIPS_REG_RA] = sim->pc;
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/* fall through */
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case MIPS_FUNCT_JR:
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sim->pc = sim->reg[ins.rs];
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break;
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case MIPS_FUNCT_MFHI:
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sim->reg[ins.rd] = sim->hi;
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break;
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case MIPS_FUNCT_MFLO:
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sim->reg[ins.rd] = sim->low;
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break;
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case MIPS_FUNCT_MTHI:
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sim->hi = sim->reg[ins.rd];
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break;
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case MIPS_FUNCT_MTLO:
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sim->low = sim->reg[ins.rd];
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break;
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case MIPS_FUNCT_SLL:
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sim->reg[ins.rd] = sim->reg[ins.rt] << ins.shamt;
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break;
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case MIPS_FUNCT_SLLV:
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sim->reg[ins.rd] = sim->reg[ins.rt] << sim->reg[ins.rs];
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break;
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case MIPS_FUNCT_SLT:
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sim->reg[ins.rd] = (int32_t)sim->reg[ins.rs] < (int32_t)sim->reg[ins.rt] ? 1 : 0;
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break;
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case MIPS_FUNCT_SLTU:
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sim->reg[ins.rd] = sim->reg[ins.rs] < sim->reg[ins.rt] ? 1 : 0;
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break;
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case MIPS_FUNCT_SRA:
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sim->reg[ins.rd] = (int32_t)sim->reg[ins.rt] >> ins.shamt;
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break;
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case MIPS_FUNCT_SRAV:
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sim->reg[ins.rd] = (int32_t)sim->reg[ins.rt] >> sim->reg[ins.rs];
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break;
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case MIPS_FUNCT_SRL:
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sim->reg[ins.rd] = sim->reg[ins.rt] >> ins.shamt;
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break;
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case MIPS_FUNCT_SRLV:
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sim->reg[ins.rd] = sim->reg[ins.rt] >> sim->reg[ins.rs];
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break;
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case MIPS_FUNCT_SUB:
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sim->reg[ins.rd] = (int32_t)sim->reg[ins.rs] -
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(int32_t)sim->reg[ins.rt];
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break;
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case MIPS_FUNCT_SUBU:
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sim->reg[ins.rd] = sim->reg[ins.rs] - sim->reg[ins.rt];
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break;
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case MIPS_FUNCT_SYSCALL:
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sim->reg[MIPS_REG_V0] = syscall(
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sim->reg[MIPS_REG_V0],
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sim->reg[MIPS_REG_A0],
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sim->reg[MIPS_REG_A1],
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sim->reg[MIPS_REG_A2],
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sim->reg[MIPS_REG_A3]
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);
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break;
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case MIPS_FUNCT_OR:
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sim->reg[ins.rd] = sim->reg[ins.rs] | sim->reg[ins.rt];
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break;
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case MIPS_FUNCT_NOR:
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sim->reg[ins.rd] = !(sim->reg[ins.rs] | sim->reg[ins.rt]);
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break;
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case MIPS_FUNCT_XOR:
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sim->reg[ins.rd] = sim->reg[ins.rs] ^ sim->reg[ins.rt];
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break;
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default:
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sim_dump(sim, "unknown funct (0b%05b)", ins.funct);
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}
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}
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static void sim_ins_regimm(struct simulator *sim,
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union mips_instruction_data ins)
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{
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switch (ins.bfunct) {
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case MIPS_FUNCT_BGEZAL:
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case MIPS_FUNCT_BGEZALL:
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sim->reg[MIPS_REG_RA] = sim->pc;
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/* fall through */
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case MIPS_FUNCT_BGEZ:
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case MIPS_FUNCT_BGEZL:
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if ((int32_t)sim->reg[ins.rs] >= 0)
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sim->pc += ins.offset << 2;
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break;
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case MIPS_FUNCT_BLTZAL:
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case MIPS_FUNCT_BLTZALL:
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sim->reg[MIPS_REG_RA] = sim->pc;
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/* fall through */
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case MIPS_FUNCT_BLTZ:
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case MIPS_FUNCT_BLTZL:
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if ((int32_t)sim->reg[ins.rs] < 0)
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sim->pc += ins.offset << 2;
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break;
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default:
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sim_dump(sim, "unknown bfunct (0b%06b)", ins.bfunct);
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}
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}
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void sim_ins(struct simulator *sim, uint32_t raw)
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{
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// get ins parts
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union mips_instruction_data ins = {
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.raw = B32(raw)
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};
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// reset zero reg
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sim->reg[MIPS_REG_ZERO] = 0;
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switch (ins.op) {
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case MIPS_OP_SPECIAL:
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sim_ins_special(sim, ins);
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break;
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case MIPS_OP_REGIMM:
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sim_ins_regimm(sim, ins);
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break;
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case MIPS_OP_ADDI:
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sim->reg[ins.rt] = (int32_t)sim->reg[ins.rs] +
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(int16_t) ins.immd;
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break;
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case MIPS_OP_ADDIU:
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sim->reg[ins.rt] = sim->reg[ins.rs] + ins.immd;
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break;
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case MIPS_OP_ANDI:
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sim->reg[ins.rt] = sim->reg[ins.rs] & ins.immd;
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break;
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case MIPS_OP_BALC:
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sim->reg[MIPS_REG_RA] = sim->pc;
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/* fall through */
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case MIPS_OP_BC:
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sim->pc += ins.offs26 << 2;
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break;
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case MIPS_OP_BEQ:
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case MIPS_OP_BEQL:
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if (sim->reg[ins.rs] == sim->reg[ins.rt])
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sim->pc += ins.offset << 2;
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break;
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case MIPS_OP_BGTZ:
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case MIPS_OP_BGTZL:
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if ((int32_t)sim->reg[ins.rs] <= 0)
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sim->pc += ins.offset << 2;
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break;
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case MIPS_OP_BLEZ:
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case MIPS_OP_BLEZL:
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if ((int32_t)sim->reg[ins.rs] <= 0)
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sim->pc += ins.offset << 2;
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break;
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case MIPS_OP_BNE:
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case MIPS_OP_BNEL:
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if (sim->reg[ins.rs] != sim->reg[ins.rt])
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sim->pc += ins.offset << 2;
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break;
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case MIPS_OP_JAL:
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sim->reg[MIPS_REG_RA] = sim->pc;
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/* fall through */
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case MIPS_OP_J:
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sim->pc = ins.target << 2;
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break;
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case MIPS_OP_LB:
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sim->reg[ins.rt] = * (int8_t *) (uintptr_t) (sim->reg[ins.rs]
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+ ins.offset);
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break;
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case MIPS_OP_LBU:
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sim->reg[ins.rt] = * (uint8_t *) (uintptr_t) (sim->reg[ins.rs]
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+ ins.offset);
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break;
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case MIPS_OP_LH:
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sim->reg[ins.rt] = * (int16_t *) (uintptr_t) (sim->reg[ins.rs]
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+ ins.offset);
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break;
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case MIPS_OP_LHU:
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sim->reg[ins.rt] = * (uint16_t *) (uintptr_t) (sim->reg[ins.rs]
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+ ins.offset);
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break;
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case MIPS_OP_LUI:
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sim->reg[ins.rt] = ins.immd << 16;
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break;
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case MIPS_OP_LW:
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sim->reg[ins.rt] = * (uint32_t *) (uintptr_t) (sim->reg[ins.rs]
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+ ins.offset);
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break;
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case MIPS_OP_SB:
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* (uint8_t *) (uintptr_t) (sim->reg[ins.rs] +
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+ ins.offset) = sim->reg[ins.rt];
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break;
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case MIPS_OP_SH:
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* (uint16_t *) (uintptr_t) (sim->reg[ins.rs] +
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ins.offset) = sim->reg[ins.rt];
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break;
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case MIPS_OP_SW:
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* (uint32_t *) (uintptr_t) (sim->reg[ins.rs] +
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ins.offset) = sim->reg[ins.rt];
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break;
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case MIPS_OP_SLTI:
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sim->reg[ins.rt] = (int32_t)sim->reg[ins.rs] <
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(int16_t)ins.immd ? 1 : 0;
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break;
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case MIPS_OP_SLTIU:
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sim->reg[ins.rt] = sim->reg[ins.rs] < ins.immd ? 1 : 0;
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break;
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case MIPS_OP_ORI:
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sim->reg[ins.rt] = sim->reg[ins.rs] | ins.immd;
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break;
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case MIPS_OP_XORI:
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sim->reg[ins.rt] = sim->reg[ins.rs] ^ ins.immd;
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break;
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default:
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sim_dump(sim, "unknown op code (0b%05b)", ins.op);
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}
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}
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