mips/lib/mips32r6.c

#include <mips32r6.h>

#define RTYPE   "rd,rs,rt"
#define ITYPE   "rt,rs,immd"
#define JTYPE   "target"
#define LOAD    "rt,offset(base)"
#define SHIFT   "rd,rt,sa"
#define SHIFTV  "rd,rt,rs"
#define BRANCH  "rs,rt,offset"
#define BRANCHZ "rs,offset"

#define INS(name, grammer) {#name, grammer, MIPS32R6_INS_ ##name, \
	/* pseudo stub */ 0, {{0, ""}}}

#define PSEUDO(name, grammer, ...) {name, grammer, __MIPS32R6_INS_NULL, \
	__VA_ARGS__ }

struct mips32_grammer mips32r6_grammers[__MIPS32R6_GRAMMER_LEN] = {

	// real instructions

	INS(ADD, RTYPE),
	INS(ADDI, ITYPE),
	INS(ADDIU, ITYPE),
	INS(ADDU, RTYPE),
	INS(AND, RTYPE),
	INS(ANDI, ITYPE),
	INS(BC1F, "cc,offset"),
	INS(BC1FL, "cc,offset"),
	INS(BC1T, "cc,offset"),
	INS(BC1TL, "cc,offset"),
	INS(BC2F, "cc,offset"),
	INS(BC2FL, "cc,offset"),
	INS(BC2T, "cc,offset"),
	INS(BC2TL, "cc,offset"),
	INS(BEQ, BRANCH),
	INS(BEQL, BRANCH),
	INS(BGEZ, BRANCHZ),
	INS(BGEZAL, BRANCHZ),
	INS(BGEZALL, BRANCHZ),
	INS(BGEZL, BRANCHZ),
	INS(BGTZ, BRANCHZ),
	INS(BGTZL, BRANCHZ),
	INS(BLEZ, BRANCHZ),
	INS(BLEZL, BRANCHZ),
	INS(BLTZ, BRANCHZ),
	INS(BLTZAL, BRANCHZ),
	INS(BLTZALL, BRANCHZ),
	INS(BLTZL, BRANCHZ),
	INS(BNE, BRANCH),
	INS(BNEL, BRANCH),
	INS(BREAK, "code"),
	INS(CACHE, "op,offset(base)"),
	INS(CFC1, "rt,fs"),
	INS(CFC2, "rt,rd"),
	INS(CLO, "rd,rs"),
	INS(CLZ, "rd,rs"),
	INS(COP2, "func"),
	INS(CTC1, "rt,fs"),
	INS(CTC2, "rt,rd"),
	INS(DERET, ""),
	INS(DI, "rt"),
	INS(DIV, RTYPE),
	INS(DIVU, RTYPE),
	INS(EI, "rt"),
	INS(ERET, ""),
	INS(EXT, "rt,rs,pos,size"),
	INS(INS, "rt,rs,pos,size"),
	INS(J, JTYPE),
	INS(JAL, JTYPE),
	INS(JALR, "rs"),
	INS(JR, "rs"),
	INS(LB, LOAD),
	INS(LBU, LOAD),
	INS(LDC1, "ft,offset(base)"),
	INS(LDC2, LOAD),
	INS(LDXC1, "fd,index(base)"),
	INS(LH, LOAD),
	INS(LHU, LOAD),
	INS(LL, LOAD),
	INS(LUI, "rt,immd"),
	INS(LUXC1, "fd,index(base)"),
	INS(LW, LOAD),
	INS(LWC1, "ft,offset(base)"),
	INS(LWC2, LOAD),
	INS(LWL, LOAD),
	INS(LWR, LOAD),
	INS(LWXC1, "fd,index(base)"),
	INS(MADD, "rs,rt"),
	INS(MADDU, "rs,rt"),
	INS(MFC0, "rt,rd"),
	INS(MFC1, "rt,fs"),
	INS(MFC2, "rt,rd"),
	INS(MFHC1, "rt,fs"),
	INS(MFHC2, "rt,rd"),
	INS(MFHI, "rd"),
	INS(MFLO, "rd"),
	INS(MOVF, "rd,rs,cc"),
	INS(MOVN, RTYPE),
	INS(MOVT, "rd,rs,cc"),
	INS(MOVZ, RTYPE),
	INS(MSUB, "rs,rt"),
	INS(MSUBU, "rs,rt"),
	INS(MTC0, "rt,rd"),
	INS(MTC1, "rt,fs"),
	INS(MTC2, "rt,rd"),
	INS(MTHC1, "rt,fs"),
	INS(MTHC2, "rt,rd"),
	INS(MTHI, "rs"),
	INS(MTLO, "rs"),
	INS(MUL, RTYPE),
	INS(MULT, "rs,rt"),
	INS(MULTU, "rs,rt"),
	INS(NOR, RTYPE),
	INS(OR, RTYPE),
	INS(ORI, ITYPE),
	INS(PREF, "hint,offset(base)"),
	INS(PREFX, "hint,index(base)"),
	INS(RDHWR, "rt,rd"),
	INS(RDPGPR, "rd,rt"),
	INS(ROTR, SHIFT),
	INS(ROTRV, SHIFTV),
	INS(SB, LOAD),
	INS(SC, LOAD),
	INS(SDBBP, "code"),
	INS(SDC1, "ft,offset(base)"),
	INS(SDC2, LOAD),
	INS(SDXC1, "fs,index(base)"),
	INS(SEB, "rd,rt"),
	INS(SEH, "rd,rt"),
	INS(SH, LOAD),
	INS(SLL, SHIFT),
	INS(SLLV, SHIFTV),
	INS(SLT, RTYPE),
	INS(SLTI, ITYPE),
	INS(SLTIU, ITYPE),
	INS(SLTU, RTYPE),
	INS(SRA, SHIFT),
	INS(SRAV, SHIFTV),
	INS(SRL, SHIFT),
	INS(SRLV, SHIFT),
	INS(SUB, RTYPE),
	INS(SUBU, RTYPE),
	INS(SUXC1, "fs,index(base)"),
	INS(SW, LOAD),
	INS(SWC1, "ft,offset(base)"),
	INS(SWC2, LOAD),
	INS(SWL, LOAD),
	INS(SWR, LOAD),
	INS(SWXC1, "fs,index(base)"),
	INS(SYNC, ""),
	INS(SYNCI, "offest(base)"),
	INS(SYSCALL, ""),
	INS(TEQ, "rs,rt"),
	INS(TEQI, "rs,immd"),
	INS(TGE, "rs,rt"),
	INS(TGEI, "rs,immd"),
	INS(TGEIU, "rs,immd"),
	INS(TGEU, "rs,rt"),
	INS(TLBP, ""),
	INS(TLBR, ""),
	INS(TLBWI, ""),
	INS(TLBWR, ""),
	INS(TLT, "rs,rt"),
	INS(TLTI, "rs,immd"),
	INS(TLTIU, "rs,immd"),
	INS(TLTU, "rs,rt"),
	INS(TNE, "rs,rt"),
	INS(TNEI, "rs,immd"),
	INS(WAIT, ""),
	INS(WRPGPR, "rd,rt"),
	INS(XOR, RTYPE),
	INS(XORI, ITYPE),

	// pseudo instructions

	PSEUDO("abs", "rd,rs", 3, {
		{MIPS32R6_INS_SRA, "rd=$at,rt=rs,sa=31"},
		{MIPS32R6_INS_ADD, "rd,rs,rt=$at"},
		{MIPS32R6_INS_XOR, "rd,rs=rd,rt=$at"},
	}),

	PSEUDO("div", "rd,rt,rs", 2, {
		{MIPS32R6_INS_DIV, "rt,rs"},
		{MIPS32R6_INS_MFLO, "rd"},
	}),

	PSEUDO("divu", "rd,rt,rs", 2, {
		{MIPS32R6_INS_DIVU, "rt,rs"},
		{MIPS32R6_INS_MFLO, "rd"},
	}),

	PSEUDO("mulo", "rd,rt,rs", 2, {
		{MIPS32R6_INS_MULT, "rt,rs"},
		{MIPS32R6_INS_MFLO, "rd"},
	}),

	PSEUDO("mulou", "rd,rt,rs", 2, {
		{MIPS32R6_INS_MULTU, "rt,rs"},
		{MIPS32R6_INS_MFLO, "rd"},
	}),

	PSEUDO("neg", "rd,rt", 1, {
		{MIPS32R6_INS_SUB, "rd,rs=$zero,rt"},
	}),

	PSEUDO("negu", "rd,rt", 1, {
		{MIPS32R6_INS_SUBU, "rd,rs=$zero,rt"},
	}),

	PSEUDO("not", "rd,rt", 1, {
		{MIPS32R6_INS_NOR, "rd,rs=$zero,rt"},
	}),

	PSEUDO("rem", "rd,rt,rs", 2, {
		{MIPS32R6_INS_DIV, "rt,rs"},
		{MIPS32R6_INS_MFHI, "rd"},
	}),

	PSEUDO("remu", "rd,rt,rs", 2, {
		{MIPS32R6_INS_DIVU, "rt,rs"},
		{MIPS32R6_INS_MFHI, "rd"},
	}),

	// TODO: rol

	// TODO: ror

	PSEUDO("subi", "rt,rs,immd", 1, {
		{MIPS32R6_INS_ADDI, "rt,rs,-immd"},
	}),

	PSEUDO("li", "rt,immd", 1, {
		{MIPS32R6_INS_ADDI, "rt,immd"}
	}),

	PSEUDO("seq", "rd,rs,rt", 3, {
		{MIPS32R6_INS_SLT, "rd,rs,rt"},
		{MIPS32R6_INS_SLT, "rd=$at,rs,rt"},
		{MIPS32R6_INS_NOR, "rd,rs=rd,rt=$at"},
	}),

	PSEUDO("sgt", "rd,rs,rt", 1, {
		{MIPS32R6_INS_SLT, "rd,rs=rt,rt=rs"},
	}),

	PSEUDO("sgtu", "rd,rs,rt", 1, {
		{MIPS32R6_INS_SLTU, "rd,rs=rt,rt=rs"},
	}),

	PSEUDO("sge", "rd,rs,rt", 2, {
		{MIPS32R6_INS_SLT, "rd,rs,rt"},
		{MIPS32R6_INS_SLTI, "rt=rd,rs=rd,immd=1"},
	}),

	PSEUDO("sgeu", "rd,rs,rt", 2, {
		{MIPS32R6_INS_SLTU, "rd,rs,rt"},
		{MIPS32R6_INS_SLTI, "rt=rd,rs=rd,immd=1"},
	}),

	PSEUDO("slte", "rd,rs,rt", 2, {
		{MIPS32R6_INS_SLT, "rd,rs=rt,rt=rs"},
		{MIPS32R6_INS_SLTI, "rt=rd,rs=rd,immd=1"},
	}),

	PSEUDO("slteu", "rd,rs,rt", 2, {
		{MIPS32R6_INS_SLTU, "rd,rs=rt,rt=rs"},
		{MIPS32R6_INS_SLTI, "rt=rd,rs=rd,immd=1"},
	}),

	PSEUDO("sne", "rd,rs,rt", 3, {
		{MIPS32R6_INS_SLT, "rd,rs,rt"},
		{MIPS32R6_INS_SLT, "rd=$at,rs,rt"},
		{MIPS32R6_INS_OR, "rd,rs=rd,rt=$at"},
	}),

	PSEUDO("jalr.hb", "rs", 1, {
		{MIPS32R6_INS_JALR, "rs,hb=1"}
	}),

	PSEUDO("jr.hb", "rs", 1, {
		{MIPS32R6_INS_JR, "rs,hb=1"}
	}),


	PSEUDO("b", "offset", 1, {
		{MIPS32R6_INS_BEQ, "rs=$zero,rt=$zero,offset"},
	}),

	PSEUDO("beqz", "rs,offset", 1, {
		{MIPS32R6_INS_BEQ, "rs,rt=$zero,offset"},
	}),

	PSEUDO("bge", "rs,rt,offset", 2, {
		{MIPS32R6_INS_SLT, "rd=$at,rs,rt"},
		{MIPS32R6_INS_BNE, "rs=$at,rt=$zero,offset"},
	}),

	PSEUDO("bgeu", "rs,rt,offset", 2, {
		{MIPS32R6_INS_SLTU, "rd=$at,rs,rt"},
		{MIPS32R6_INS_BNE, "rs=$at,rt=$zero,offset"},
	}),

	PSEUDO("bge", "rs,rt,offset", 2, {
		{MIPS32R6_INS_SLT, "rd=$at,rs,rt"},
		{MIPS32R6_INS_BEQ, "rs=$at,rt=$zero,offset"},
	}),

	PSEUDO("bgeu", "rs,rt,offset", 2, {
		{MIPS32R6_INS_SLTU, "rd=$at,rs,rt"},
		{MIPS32R6_INS_BEQ, "rs=$at,rt=$zero,offset"},
	}),

	PSEUDO("ble", "rs,rt,offset", 2, {
		{MIPS32R6_INS_SLT, "rd=$at,rs=rt,rt=rs"},
		{MIPS32R6_INS_BEQ, "rs=$at,rt=$zero,offset"},
	}),

	PSEUDO("bleu", "rs,rt,offset", 2, {
		{MIPS32R6_INS_SLT, "rd=$at,rs=rt,rt=rs"},
		{MIPS32R6_INS_BEQ, "rs=$at,rt=$zero,offset"},
	}),

	PSEUDO("blt", "rs,rt,offset", 2, {
		{MIPS32R6_INS_SLT, "rd=$at,rs,rt"},
		{MIPS32R6_INS_BNE, "rs=$at,rt=$zero,offset"},
	}),

	PSEUDO("bltu", "rs,rt,offset", 2, {
		{MIPS32R6_INS_SLTU, "rd=$at,rs,rt"},
		{MIPS32R6_INS_BNE, "rs=$at,rt=$zero,offset"},
	}),

	PSEUDO("bnez", "rs,offset", 1, {
		{MIPS32R6_INS_BNE, "rs,rt=$zero,offset"},
	}),

	// TODO: ld

	// TODO: load unaligned

	// TODO: store unaligned

	PSEUDO("la", "rt,target", 2, {
		{MIPS32R6_INS_LUI, "rt=$at,hi"},
		{MIPS32R6_INS_ORI, "rt,rs=$at,lo"},
	}),

	PSEUDO("move", "rd,rs", 1, {
		{MIPS32R6_INS_OR, "rd,rs"}
	}),

	PSEUDO("nop", "", 1, {
		{MIPS32R6_INS_SLL, ""},
	}),

	PSEUDO("ssnop", "", 1, {
		{MIPS32R6_INS_SLL, "sa=1"},
	}),

	PSEUDO("ehb", "", 1, {
		{MIPS32R6_INS_SLL, "sa=3"}
	}),
};

#define MIPS_INS(ins, ...) \
	[MIPS32R6_INS_ ##ins] = { __VA_ARGS__ },

union mips32_instruction mips32r6_instructions[__MIPS32R6_INS_LEN] = {
/* ADD - add */
MIPS_INS(ADD, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_ADD)

/* ADDI - add immediate */
MIPS_INS(ADDI, .op = MIPS32R6_OP_ADDI)

/* ADDIU - add immediate unsigned */
MIPS_INS(ADDIU, .op = MIPS32R6_OP_ADDIU)

/* ADDU - add unsigned */
MIPS_INS(ADDU, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_ADDU)

/* AND - and */
MIPS_INS(AND, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_AND)

/* ANDI - and immediate */
MIPS_INS(ANDI, .op = MIPS32R6_OP_ANDI)

/* BC1F - branch on cop1 false */
MIPS_INS(BC1F, .op = MIPS32R6_OP_COP1, .cfunct = MIPS32R6_FUNCT_BC,
	 .nd = 0, .tf = 0)

/* BC1FL - branch on cop1 false likely */
MIPS_INS(BC1FL, .op = MIPS32R6_OP_COP1, .cfunct = MIPS32R6_FUNCT_BC,
	 .nd = 1, .tf = 0)

/* BC1T - branch on cop1 true */
MIPS_INS(BC1T, .op = MIPS32R6_OP_COP1, .cfunct = MIPS32R6_FUNCT_BC,
	 .nd = 0, .tf = 1)

/* BC1TL - branch on cop1 true likely */
MIPS_INS(BC1TL, .op = MIPS32R6_OP_COP1, .cfunct = MIPS32R6_FUNCT_BC,
	 .nd = 1, .tf = 1)

/* BC2F - branch on cop1 false */
MIPS_INS(BC2F, .op = MIPS32R6_OP_COP2, .cfunct = MIPS32R6_FUNCT_BC,
	 .nd = 0, .tf = 0)

/* BC2FL - branch on cop1 false likely */
MIPS_INS(BC2FL, .op = MIPS32R6_OP_COP2, .cfunct = MIPS32R6_FUNCT_BC,
	 .nd = 1, .tf = 0)

/* BC2T - branch on cop1 true */
MIPS_INS(BC2T, .op = MIPS32R6_OP_COP2, .cfunct = MIPS32R6_FUNCT_BC,
	 .nd = 0, .tf = 1)

/* BC2TL - branch on cop1 true likely */
MIPS_INS(BC2TL, .op = MIPS32R6_OP_COP2, .cfunct = MIPS32R6_FUNCT_BC,
	 .nd = 1, .tf = 1)

/* BEQ - branch on equal */
MIPS_INS(BEQ, .op = MIPS32R6_OP_BEQ)

/* BEQL - branch on equal likely */
MIPS_INS(BEQL, .op = MIPS32R6_OP_BEQL)

/* BGEZ - branch on greater than or equal to zero */
MIPS_INS(BGEZ, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_BGEZ)

/* BGEZAL - branch on greater than or equal to zero and link */
MIPS_INS(BGEZAL, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_BGEZAL)

/* BGEZALL - branch on greater than or equal to zero and link likely */
MIPS_INS(BGEZALL, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_BGEZALL)

/* BGEZL - branch on greater than or equal to zero likely */
MIPS_INS(BGEZL, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_BGEZL)

/* BGTZ - branch on greater than zero */
MIPS_INS(BGTZ, .op = MIPS32R6_OP_BGTZ)

/* BGTZL - branch on greater than zero likely */
MIPS_INS(BGTZL, .op = MIPS32R6_OP_BGTZL)

/* BLEZ - branch on less than or equal to zero */
MIPS_INS(BLEZ, .op = MIPS32R6_OP_BLEZ)

/* BLEZL - branch on less than or equal to zero likely */
MIPS_INS(BLEZL, .op = MIPS32R6_OP_BLEZL)

/* BLTZ - branch on less than zero */
MIPS_INS(BLTZ, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_BLTZ)

/* BLTZAL - branch on less than zero and link */
MIPS_INS(BLTZAL, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_BLTZAL)

/* BLTZALL - branch on less than zero and link likely */
MIPS_INS(BLTZALL, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_BLTZALL)

/* BLTZL - branch on less than zero likely */
MIPS_INS(BLTZL, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_BLTZL)

/* BNE - branch on not equal */
MIPS_INS(BNE, .op = MIPS32R6_OP_BNE)

/* BNEL - branch on not equal likely */
MIPS_INS(BNEL, .op = MIPS32R6_OP_BNEL)

/* BREAK - breakpoint */
MIPS_INS(BREAK, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_BREAK)

/* CACHE - perform cache operation */
MIPS_INS(CACHE, .op = MIPS32R6_OP_CACHE)

/* CFC1 - move control word from floating point */
MIPS_INS(CFC1, .op = MIPS32R6_OP_COP1, .cfunct = MIPS32R6_FUNCT_CF)

/* CFC2 - move control word from coprocessor 2 */
MIPS_INS(CFC2, .op = MIPS32R6_OP_COP2, .cfunct = MIPS32R6_FUNCT_CF)

/* CLO - count leading ones */
MIPS_INS(CLO, .op = MIPS32R6_OP_SPECIAL2, .funct = MIPS32R6_FUNCT_CLO)

/* CLZ - count leading zeros */
MIPS_INS(CLZ, .op = MIPS32R6_OP_SPECIAL2, .funct = MIPS32R6_FUNCT_CLZ)

/* COP2 - coprocessor operation to coprocessor 2 */
MIPS_INS(COP2, .op = MIPS32R6_OP_COP2, .c0 = 1)

/* CTC1 - move control word to floating point */
MIPS_INS(CTC1, .op = MIPS32R6_OP_COP1, .cfunct = MIPS32R6_FUNCT_CT)

/* CTC2 - move control word to coprocessor 2 */
MIPS_INS(CTC2, .op = MIPS32R6_OP_COP2, .cfunct = MIPS32R6_FUNCT_CT)

/* DERET - debug exception return */
MIPS_INS(DERET, .op = MIPS32R6_OP_COP0, .c0 = 1, .funct = MIPS32R6_FUNCT_DERET)

/* DI - disable interupts */
MIPS_INS(DI, .op = MIPS32R6_OP_COP0, .cfunct = MIPS32R6_FUNCT_MFMC0,
	 .rd = 12, .sc = 0)

/* DIV - divide */
MIPS_INS(DIV, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_DIV)

/* DIVU - divide unsigned */
MIPS_INS(DIVU, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_DIVU)

/* EI - enable interupts */
MIPS_INS(EI, .op = MIPS32R6_OP_COP0, .cfunct = MIPS32R6_FUNCT_MFMC0,
	 .rd = 12, .sc = 1)

/* ERET - exception return */
MIPS_INS(ERET, .op = MIPS32R6_OP_COP0, .c0 = 1, .funct = MIPS32R6_FUNCT_ERET)

/* ERT - extract bit field */
MIPS_INS(EXT, .op = MIPS32R6_OP_SPECIAL3, .funct = MIPS32R6_FUNCT_EXT)

/* INS - insert bit field */
MIPS_INS(INS, .op = MIPS32R6_OP_SPECIAL3, .funct = MIPS32R6_FUNCT_INS)

/* J - jump */
MIPS_INS(J, .op = MIPS32R6_OP_J)

/* JAL - jump and link */
MIPS_INS(JAL, .op = MIPS32R6_OP_JAL)

/* JALR - jump and link register */
MIPS_INS(JALR, .rd = MIPS32_REG_RA, .op = MIPS32R6_OP_SPECIAL,
	 .funct = MIPS32R6_FUNCT_JALR)

/* JR - jump register */
MIPS_INS(JR, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_JR)

/* LB - load byte */
MIPS_INS(LB, .op = MIPS32R6_OP_LB)

/* LBU - load byte unsigned */
MIPS_INS(LBU, .op = MIPS32R6_OP_LBU)

/* LDC1 - load doubleword floating point */
MIPS_INS(LDC1, .op = MIPS32R6_OP_LDC1)

/* LDC2 - load doubleword cop2 */
MIPS_INS(LDC2, .op = MIPS32R6_OP_LDC2)

/* LDXC1 - load doubleword indexed to floating point */
MIPS_INS(LDXC1, .op = MIPS32R6_OP_COP1X, .funct = MIPS32R6_FUNCT_LDXC1)

/* LH - load half */
MIPS_INS(LH, .op = MIPS32R6_OP_LH)

/* LHU - load half unsigned */
MIPS_INS(LHU, .op = MIPS32R6_OP_LHU)

/* LK - load linked */
MIPS_INS(LL, .op = MIPS32R6_OP_LL)

/* LUI - load upper immediate */
MIPS_INS(LUI, .op = MIPS32R6_OP_LUI)

/* LUXC1 - load doubleword indexed unaligned to floating point */
MIPS_INS(LUXC1, .op = MIPS32R6_OP_COP1X, .funct = MIPS32R6_FUNCT_LUXC1)

/* LW - load word */
MIPS_INS(LW, .op = MIPS32R6_OP_LW)

/* LDC1 - load word floating point */
MIPS_INS(LWC1, .op = MIPS32R6_OP_LWC1)

/* LDC2 - load eword cop2 */
MIPS_INS(LWC2, .op = MIPS32R6_OP_LWC2)

/* LWL - load word left */
MIPS_INS(LWL, .op = MIPS32R6_OP_LWL)

/* LWR - load word right */
MIPS_INS(LWR, .op = MIPS32R6_OP_LWR)

/* LWXC1 - load word indexed to floating point */
MIPS_INS(LWXC1, .op = MIPS32R6_OP_COP1X, .funct = MIPS32R6_FUNCT_LWXC1)

/* MADD - multiply and add words to hi,lo */
MIPS_INS(MADD, .op = MIPS32R6_OP_SPECIAL2, .funct = MIPS32R6_FUNCT_MADD)

/* MADDU - multiply and add unsigned words to hi,lo */
MIPS_INS(MADDU, .op = MIPS32R6_OP_SPECIAL2, .funct = MIPS32R6_FUNCT_MADDU)

/* MFC0 - move from cop0 */
MIPS_INS(MFC0, .op = MIPS32R6_OP_COP0, .cfunct = MIPS32R6_FUNCT_MF)

/* MFC1 - move from floating point */
MIPS_INS(MFC1, .op = MIPS32R6_OP_COP1, .cfunct = MIPS32R6_FUNCT_MF)

/* MFC2 - move from cop2 */
MIPS_INS(MFC2, .op = MIPS32R6_OP_COP0, .cfunct = MIPS32R6_FUNCT_MF)

/* MFHC1 - move word from high half of floating point register */
MIPS_INS(MFHC1, .op = MIPS32R6_OP_COP1, .cfunct = MIPS32R6_FUNCT_MFH)

/* MFHC2 - move word from high half of cop2 */
MIPS_INS(MFHC2, .op = MIPS32R6_OP_COP2, .cfunct = MIPS32R6_FUNCT_MFH)

/* MFHI - move from hi register */
MIPS_INS(MFHI, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_MFHI)

/* MFLO - move from lo register */
MIPS_INS(MFLO, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_MFLO)

/* MOVF - move on floating point false */
MIPS_INS(MOVF, .op = MIPS32R6_OP_SPECIAL, .tf = 0,
	 .funct = MIPS32R6_FUNCT_MOVCL)

/* MOVN - move conditional on non zero */
MIPS_INS(MOVN, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_MOVN)

/* MOVT - move on floating point true */
MIPS_INS(MOVT, .op = MIPS32R6_OP_SPECIAL, .tf = 1,
	 .funct = MIPS32R6_FUNCT_MOVCL)

/* MOVZ - move conditional on zero */
MIPS_INS(MOVZ, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_MOVZ)

/* MSUB - multiply and add words to hi,lo */
MIPS_INS(MSUB, .op = MIPS32R6_OP_SPECIAL2, .funct = MIPS32R6_FUNCT_MSUB)

/* MSUBU - multiply and add unsigned words to hi,lo */
MIPS_INS(MSUBU, .op = MIPS32R6_OP_SPECIAL2, .funct = MIPS32R6_FUNCT_MSUBU)

/* MTC0 - move to cop0 */
MIPS_INS(MTC0, .op = MIPS32R6_OP_COP0, .cfunct = MIPS32R6_FUNCT_MT)

/* MTC1 - move to floating point */
MIPS_INS(MTC1, .op = MIPS32R6_OP_COP1, .cfunct = MIPS32R6_FUNCT_MT)

/* MTC2 - move to cop2 */
MIPS_INS(MTC2, .op = MIPS32R6_OP_COP0, .cfunct = MIPS32R6_FUNCT_MT)

/* MTHC1 - move word to high half of floating point register */
MIPS_INS(MTHC1, .op = MIPS32R6_OP_COP1, .cfunct = MIPS32R6_FUNCT_MTH)

/* MTHC2 - move word to high half of cop2 */
MIPS_INS(MTHC2, .op = MIPS32R6_OP_COP2, .cfunct = MIPS32R6_FUNCT_MTH)

/* MTHI - move to hi register */
MIPS_INS(MTHI, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_MTHI)

/* MTLO - move to lo register */
MIPS_INS(MTLO, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_MTLO)

/* MUL - multiply word to GPR */
MIPS_INS(MUL, .op = MIPS32R6_OP_SPECIAL2, .funct = MIPS32R6_FUNCT_MUL)

/* MULT - multiply word */
MIPS_INS(MULT, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_MULT)

/* MULTU - multiply unsigned word */
MIPS_INS(MULTU, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_MULTU)

/* NOR - not or */
MIPS_INS(NOR, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_NOR)

/* OR - or */
MIPS_INS(OR, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_OR)

/* ORI - or imemdiate */
MIPS_INS(ORI, .op = MIPS32R6_OP_ORI)

/* PREF - prefetch */
MIPS_INS(PREF, .op = MIPS32R6_OP_PREF)

/* PREFX - prefetch indexed */
MIPS_INS(PREFX, .op = MIPS32R6_OP_COP1X, .funct = MIPS32R6_FUNCT_PREFX)

/* RDHWR - read hardware register */
MIPS_INS(RDHWR, .op = MIPS32R6_OP_SPECIAL3, .funct = MIPS32R6_FUNCT_RDHWR)

/* RDPGPR - read gpr from previous shadow set */
MIPS_INS(RDPGPR, .op = MIPS32R6_OP_COP0, .cfunct = MIPS32R6_FUNCT_RDPGPR)

/* ROTR - rotate word right */
MIPS_INS(ROTR, .op = MIPS32R6_OP_SPECIAL, .r = 1, .funct = MIPS32R6_FUNCT_SRL)

/* ROTRV - rotate word right variable */
MIPS_INS(ROTRV, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SRLV,
	 .rv = 1)

/* SB - store byte */
MIPS_INS(SB, .op = MIPS32R6_OP_SB)

/* SC - store conditional word */
MIPS_INS(SC, .op = MIPS32R6_OP_SC)

/* SDBBP - software debug breakpoint */
MIPS_INS(SDBBP, .op = MIPS32R6_OP_SPECIAL2, .funct = MIPS32R6_FUNCT_SDBBP)

/* SDC1 - store doubleword floating point */
MIPS_INS(SDC1, .op = MIPS32R6_OP_SDC1)

/* SDC2 - store doubleword cop2 */
MIPS_INS(SDC2, .op = MIPS32R6_OP_SDC2)

/* SDXC1 - store doubleword indexed from floating point */
MIPS_INS(SDXC1, .op = MIPS32R6_OP_COP1X, .funct = MIPS32R6_FUNCT_SDXC1)

/* SEB - sign extend byte */
MIPS_INS(SEB, .op = MIPS32R6_OP_SPECIAL3, .shamt = MIPS32R6_FUNCT_SEB,
	 .funct = MIPS32R6_FUNCT_BSHFL)

/* SEH - sign extend halfword */
MIPS_INS(SEH, .op = MIPS32R6_OP_SPECIAL3, .shamt = MIPS32R6_FUNCT_SEH,
	 .funct = MIPS32R6_FUNCT_BSHFL)

/* SH - store half */
MIPS_INS(SH, .op = MIPS32R6_OP_SH)

/* SLL - shift left logical */
MIPS_INS(SLL, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SLL)

/* SLLV - shift left logical variable */
MIPS_INS(SLLV, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SLLV)

/* SLT - set less then */
MIPS_INS(SLT, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SLT)

/* SLTI - set less then immediate */
MIPS_INS(SLTI, .op = MIPS32R6_OP_SLTI)

/* SLTIU - set less then imemdiate unsigned */
MIPS_INS(SLTIU, .op = MIPS32R6_OP_SLTIU)

/* SLTU - set less than unsigned */
MIPS_INS(SLTU, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SLTU)

/* SRA - shift right arithmetic */
MIPS_INS(SRA, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SRA)

/* SRAV - shift right arithmetic variable */
MIPS_INS(SRAV, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SRAV)

/* SRL - shift right logical */
MIPS_INS(SRL, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SRL)

/* SRLV - shift right logical variable */
MIPS_INS(SRLV, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SRLV)

/* SUB - subtract */
MIPS_INS(SUB, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SUB)

/* SUBU - subtract unsigned */
MIPS_INS(SUBU, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SUBU)

/* SUXC1 - store doubleword indexed unaligned from floating point */
MIPS_INS(SUXC1, .op = MIPS32R6_OP_COP1X, .funct = MIPS32R6_FUNCT_SUXC1)

/* SW - store word */
MIPS_INS(SW, .op = MIPS32R6_OP_SW)

/* SWC1 - store word floating point */
MIPS_INS(SWC1, .op = MIPS32R6_OP_SWC1)

/* SWC2 - store eword cop2 */
MIPS_INS(SWC2, .op = MIPS32R6_OP_SWC2)

/* SWL - store word left */
MIPS_INS(SWL, .op = MIPS32R6_OP_SWL)

/* SWR - store word right */
MIPS_INS(SWR, .op = MIPS32R6_OP_SWR)

/* SWXC1 - store word indexed from floating point */
MIPS_INS(SWXC1, .op = MIPS32R6_OP_COP1X, .funct = MIPS32R6_FUNCT_SWXC1)

/* SYNC - synchronize shared memory */
MIPS_INS(SYNC, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SYNC)

/* SYNCI - synchronize caches to make instruction writes effective */
MIPS_INS(SYNCI, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_SYNCI)

/* SYSCALL - syscall */
MIPS_INS(SYSCALL, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_SYSCALL)

/* TEQ - trap if equal */
MIPS_INS(TEQ, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_TEQ)

/* TEQI - trap if equal immediate */
MIPS_INS(TEQI, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_TEQI)

/* TGE - trap if greater or equal */
MIPS_INS(TGE, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_TGE)

/* TGEI - trap if greater or equal immediate */
MIPS_INS(TGEI, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_TGEI)

/* TGEIU - trap if greater or equal immediate unsigned */
MIPS_INS(TGEIU, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_TGEIU)

/* TGEU - trap if greater or equal unsigned */
MIPS_INS(TGEU, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_TGEU)

/* TLBP - probe TLB for matching entry */
MIPS_INS(TLBP, .op = MIPS32R6_OP_COP0, .c0 = 1, .funct = MIPS32R6_FUNCT_TLBP)

/* TLBR - read indexed TLB entry */
MIPS_INS(TLBR, .op = MIPS32R6_OP_COP0, .c0 = 1, .funct = MIPS32R6_FUNCT_TLBR)

/* TLBWI - write indexed TLB entry */
MIPS_INS(TLBWI, .op = MIPS32R6_OP_COP0, .c0 = 1, .funct = MIPS32R6_FUNCT_TLBWI)

/* TLBWR - write random TLB entry */
MIPS_INS(TLBWR, .op = MIPS32R6_OP_COP0, .c0 = 1, .funct = MIPS32R6_FUNCT_TLBWR)

/* TLT - trap if less then */
MIPS_INS(TLT, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_TLT)

/* TLTI - trap if less then immediate */
MIPS_INS(TLTI, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_TLTI)

/* TLTIU - trap if less then immediate unsigned */
MIPS_INS(TLTIU, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_TLTIU)

/* TLTU - trap if less then unsigned */
MIPS_INS(TLTU, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_TLTU)

/* TNE - trap if not equal */
MIPS_INS(TNE, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_TNE)

/* TNEI - trap if not equal immediate */
MIPS_INS(TNEI, .op = MIPS32R6_OP_REGIMM, .bfunct = MIPS32R6_FUNCT_TNEI)

/* WAIT - enter standby mode */
MIPS_INS(WAIT, .op = MIPS32R6_OP_COP0, .c0 = 1, .funct = MIPS32R6_FUNCT_WAIT)

/* WRPGRP - write to GPR in previous shadow set */
MIPS_INS(WRPGPR, .op = MIPS32R6_OP_COP0, .cfunct = MIPS32R6_FUNCT_WRPGPR)

/* WSBH - word swap bytes within halfwords */
MIPS_INS(WSBH, .op = MIPS32R6_OP_SPECIAL3, .funct = MIPS32R6_FUNCT_BSHFL,
	 .shamt = MIPS32R6_FUNCT_WSBH)

/* XOR - exclusive or */
MIPS_INS(XOR, .op = MIPS32R6_OP_SPECIAL, .funct = MIPS32R6_FUNCT_XOR)

/* XORI - exclusive or immediate */
MIPS_INS(XORI, .op = MIPS32R6_OP_XORI)
};

#undef MIPS_INS