mips/msim/ins.c

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#include <melf.h>
#include <stdint.h>
#include <unistd.h>
#include <merror.h>
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#include <mips32r6.h>
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#include "sim.h"
/* sign extension */
#define SE(n) ((uint32_t)(int16_t)(n))
/* sign extension 64bit */
#define SE64(n) ((uint64_t)(int32_t)(n))
/* signed sign extension 64bit */
#define SSE64(n) ((int64_t)(int32_t)(n))
/* shifted sign extention */
#define SSE(n, s) (SE(n) << (s))
/* zero extension */
#define ZE(n) ((uint32_t)(uint16_t)(n))
/* get vaddr from offset and base */
#define VADDR(sim, ins) \
((sim->reg[ins.rs] /* base */) + \
(SE(ins.offset) /* offset */))
/* gets the low 32 bits of a 64 bit value */
#define LO(n) (((1ULL << 32) - 1) & (n))
/* gets the hi 32 bits of a 64 bit value */
#define HI(n) ((n) >> 32)
/* convert to a pointer */
#define PTR(ptr, type) ((type *)(uintptr_t)(ptr))
static void sim_delay_slot(struct simulator *sim)
{
if (sim->args->jdelay == false)
return;
uint32_t ins = * (uint32_t *) (uintptr_t) sim->pc;
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union mips32_instruction data = { .raw = B32(ins) };
sim->pc += 4;
switch (data.op) {
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case MIPS32R6_OP_REGIMM:
case MIPS32R6_OP_J:
case MIPS32R6_OP_JAL:
case MIPS32R6_OP_JALX:
case MIPS32R6_OP_BEQ:
case MIPS32R6_OP_BEQL:
case MIPS32R6_OP_BNE:
case MIPS32R6_OP_BNEL:
case MIPS32R6_OP_BGTZ:
case MIPS32R6_OP_BGTZL:
case MIPS32R6_OP_BLEZ:
case MIPS32R6_OP_BLEZL:
sim_dump(sim, "attempted to execute jump instruction in delay"
"slot (0b%05b)", data.op);
default:
}
sim_ins(sim, ins);
}
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static void sim_ins_special_sop30(struct simulator *sim,
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union mips32_instruction ins)
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{
switch (ins.shamt) {
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case MIPS32R6_SOP30_MUL:
sim->reg[ins.rd] = (SSE64(sim->reg[ins.rs]) *
SSE64(sim->reg[ins.rt])) >> 0;
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break;
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case MIPS32R6_SOP30_MUH:
sim->reg[ins.rd] = (SSE64(sim->reg[ins.rs]) *
SSE64(sim->reg[ins.rt])) >> 32;
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break;
default:
sim_dump(sim, "unknown sop30 funct (0b%06b)", ins.shamt);
}
}
static void sim_ins_special_sop31(struct simulator *sim,
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union mips32_instruction ins)
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{
switch (ins.shamt) {
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case MIPS32R6_SOP31_MULU:
sim->reg[ins.rd] = (SE64(sim->reg[ins.rs]) *
SE64(sim->reg[ins.rt])) >> 0;
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break;
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case MIPS32R6_SOP31_MUHU:
sim->reg[ins.rd] = (SE64(sim->reg[ins.rs]) *
SE64(sim->reg[ins.rt])) >> 32;
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break;
default:
sim_dump(sim, "unknown sop31 funct (0b%06b)", ins.shamt);
}
}
static void sim_ins_special_sop32(struct simulator *sim,
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union mips32_instruction ins)
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{
switch (ins.shamt) {
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case MIPS32R6_SOP32_DIV:
sim->reg[ins.rd] = (signed) sim->reg[ins.rs] /
(signed) sim->reg[ins.rt];
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break;
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case MIPS32R6_SOP32_MOD:
sim->reg[ins.rd] = (signed) sim->reg[ins.rs] %
(signed) sim->reg[ins.rt];
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break;
default:
sim_dump(sim, "unknown sop32 funct (0b%06b)", ins.shamt);
}
}
static void sim_ins_special_sop33(struct simulator *sim,
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union mips32_instruction ins)
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{
switch (ins.shamt) {
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case MIPS32R6_SOP33_DIVU:
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sim->reg[ins.rd] = sim->reg[ins.rs] / sim->reg[ins.rt];
break;
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case MIPS32R6_SOP33_MODU:
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sim->reg[ins.rd] = sim->reg[ins.rs] % sim->reg[ins.rt];
break;
default:
sim_dump(sim, "unknown sop33 funct (0b%06b)", ins.shamt);
}
}
static void sim_ins_special(struct simulator *sim,
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union mips32_instruction ins)
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{
switch (ins.funct) {
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case MIPS32R6_FUNCT_ADD:
// TODO: trap on overflow
sim->reg[ins.rd] = sim->reg[ins.rs] + sim->reg[ins.rt];
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break;
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case MIPS32R6_FUNCT_ADDU:
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sim->reg[ins.rd] = sim->reg[ins.rs] + sim->reg[ins.rt];
break;
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case MIPS32R6_FUNCT_AND:
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sim->reg[ins.rd] = sim->reg[ins.rs] & sim->reg[ins.rt];
break;
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case MIPS32R6_FUNCT_SOP30:
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sim_ins_special_sop30(sim, ins);
break;
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case MIPS32R6_FUNCT_SOP31:
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sim_ins_special_sop31(sim, ins);
break;
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case MIPS32R6_FUNCT_SOP32:
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sim_ins_special_sop32(sim, ins);
break;
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case MIPS32R6_FUNCT_SOP33:
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sim_ins_special_sop33(sim, ins);
break;
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case MIPS32R6_FUNCT_JALR:
sim->reg[ins.rd] = sim->pc + 4;
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/* fall through */
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case MIPS32R6_FUNCT_JR:
sim_delay_slot(sim);
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sim->pc = sim->reg[ins.rs];
break;
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case MIPS32R6_FUNCT_MFHI:
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sim->reg[ins.rd] = sim->hi;
break;
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case MIPS32R6_FUNCT_MFLO:
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sim->reg[ins.rd] = sim->low;
break;
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case MIPS32R6_FUNCT_MTHI:
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sim->hi = sim->reg[ins.rd];
break;
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case MIPS32R6_FUNCT_MTLO:
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sim->low = sim->reg[ins.rd];
break;
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case MIPS32R6_FUNCT_SLL:
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sim->reg[ins.rd] = sim->reg[ins.rt] << ins.shamt;
break;
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case MIPS32R6_FUNCT_SLLV:
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sim->reg[ins.rd] = sim->reg[ins.rt] << sim->reg[ins.rs];
break;
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case MIPS32R6_FUNCT_SLT:
sim->reg[ins.rd] = (signed) sim->reg[ins.rs] <
(signed) sim->reg[ins.rt] ? 1 : 0;
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break;
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case MIPS32R6_FUNCT_SLTU:
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sim->reg[ins.rd] = sim->reg[ins.rs] < sim->reg[ins.rt] ? 1 : 0;
break;
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case MIPS32R6_FUNCT_SRA:
sim->reg[ins.rd] = (signed) sim->reg[ins.rt] >> ins.shamt;
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break;
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case MIPS32R6_FUNCT_SRAV:
sim->reg[ins.rd] = (signed) sim->reg[ins.rt] >>
sim->reg[ins.rs];
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break;
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case MIPS32R6_FUNCT_SRL:
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sim->reg[ins.rd] = sim->reg[ins.rt] >> ins.shamt;
break;
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case MIPS32R6_FUNCT_SRLV:
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sim->reg[ins.rd] = sim->reg[ins.rt] >> sim->reg[ins.rs];
break;
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case MIPS32R6_FUNCT_SUB:
// TODO: trap on overflow
sim->reg[ins.rd] = sim->reg[ins.rs] - sim->reg[ins.rt];
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break;
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case MIPS32R6_FUNCT_SUBU:
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sim->reg[ins.rd] = sim->reg[ins.rs] - sim->reg[ins.rt];
break;
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case MIPS32R6_FUNCT_SYSCALL:
sim->reg[MIPS32_REG_V0] = syscall(
sim->reg[MIPS32_REG_V0],
sim->reg[MIPS32_REG_A0],
sim->reg[MIPS32_REG_A1],
sim->reg[MIPS32_REG_A2],
sim->reg[MIPS32_REG_A3]
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);
break;
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case MIPS32R6_FUNCT_OR:
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sim->reg[ins.rd] = sim->reg[ins.rs] | sim->reg[ins.rt];
break;
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case MIPS32R6_FUNCT_NOR:
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sim->reg[ins.rd] = !(sim->reg[ins.rs] | sim->reg[ins.rt]);
break;
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case MIPS32R6_FUNCT_XOR:
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sim->reg[ins.rd] = sim->reg[ins.rs] ^ sim->reg[ins.rt];
break;
default:
sim_dump(sim, "unknown funct (0b%05b)", ins.funct);
}
}
static void sim_ins_regimm(struct simulator *sim,
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union mips32_instruction ins)
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{
uint32_t pc = sim->pc;
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switch (ins.bfunct) {
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case MIPS32R6_FUNCT_BGEZAL:
case MIPS32R6_FUNCT_BGEZALL:
sim->reg[MIPS32_REG_RA] = sim->pc + 4;
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/* fall through */
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case MIPS32R6_FUNCT_BGEZ:
case MIPS32R6_FUNCT_BGEZL:
sim_delay_slot(sim);
if ((signed) sim->reg[ins.rs] >= 0)
sim->pc = pc + SSE(ins.offset, 2);
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break;
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case MIPS32R6_FUNCT_BLTZAL:
case MIPS32R6_FUNCT_BLTZALL:
sim->reg[MIPS32_REG_RA] = sim->pc + 4;
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/* fall through */
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case MIPS32R6_FUNCT_BLTZ:
case MIPS32R6_FUNCT_BLTZL:
sim_delay_slot(sim);
if ((signed) sim->reg[ins.rs] < 0)
sim->pc = pc + SSE(ins.offset, 2);
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break;
default:
sim_dump(sim, "unknown branch funct (0b%06b)", ins.bfunct);
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}
}
void sim_ins(struct simulator *sim, uint32_t raw)
{
// get ins parts
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union mips32_instruction ins = {
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.raw = B32(raw)
};
uint32_t pc = sim->pc;
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// reset zero reg
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sim->reg[MIPS32_REG_ZERO] = 0;
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switch (ins.op) {
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case MIPS32R6_OP_SPECIAL:
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sim_ins_special(sim, ins);
break;
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case MIPS32R6_OP_REGIMM:
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sim_ins_regimm(sim, ins);
break;
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case MIPS32R6_OP_ADDI:
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sim->reg[ins.rt] = (int32_t)sim->reg[ins.rs] +
SE(ins.immd);
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break;
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case MIPS32R6_OP_ADDIU:
sim->reg[ins.rt] = sim->reg[ins.rs] + SE(ins.immd);
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break;
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case MIPS32R6_OP_ANDI:
sim->reg[ins.rt] = sim->reg[ins.rs] & ZE(ins.immd);
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break;
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case MIPS32R6_OP_BALC:
sim->reg[MIPS32_REG_RA] = sim->pc;
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/* fall through */
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case MIPS32R6_OP_BC:
sim->pc += SSE(ins.offs26, 2);
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break;
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case MIPS32R6_OP_BEQ:
case MIPS32R6_OP_BEQL:
sim_delay_slot(sim);
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if (sim->reg[ins.rs] == sim->reg[ins.rt])
sim->pc = pc + SSE(ins.offset, 2);
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break;
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case MIPS32R6_OP_BGTZ:
case MIPS32R6_OP_BGTZL:
sim_delay_slot(sim);
if ((signed) sim->reg[ins.rs] <= 0)
sim->pc = pc + SSE(ins.offset, 2);
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break;
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case MIPS32R6_OP_BLEZ:
case MIPS32R6_OP_BLEZL:
sim_delay_slot(sim);
if ((signed) sim->reg[ins.rs] <= 0)
sim->pc = pc + SSE(ins.offset, 2);
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break;
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case MIPS32R6_OP_BNE:
case MIPS32R6_OP_BNEL:
sim_delay_slot(sim);
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if (sim->reg[ins.rs] != sim->reg[ins.rt])
sim->pc = pc + SSE(ins.offset, 2);
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break;
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case MIPS32R6_OP_JAL:
sim->reg[MIPS32_REG_RA] = sim->pc + 4;
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/* fall through */
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case MIPS32R6_OP_J:
sim_delay_slot(sim);
sim->pc &= 0xF0000000;
sim->pc |= ins.target << 2;
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break;
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case MIPS32R6_OP_LB:
sim->reg[ins.rt] = *PTR(VADDR(sim, ins), int8_t);
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break;
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case MIPS32R6_OP_LBU:
sim->reg[ins.rt] = *PTR(VADDR(sim, ins), uint8_t);
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break;
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case MIPS32R6_OP_LH:
sim->reg[ins.rt] = *PTR(VADDR(sim, ins), int16_t);
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break;
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case MIPS32R6_OP_LHU:
sim->reg[ins.rt] = *PTR(VADDR(sim, ins), uint16_t);
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break;
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case MIPS32R6_OP_LUI:
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sim->reg[ins.rt] = ins.immd << 16;
break;
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case MIPS32R6_OP_LW:
sim->reg[ins.rt] = *PTR(VADDR(sim, ins), uint32_t);
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break;
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case MIPS32R6_OP_SB:
*PTR(VADDR(sim, ins), uint8_t) = sim->reg[ins.rt];
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break;
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case MIPS32R6_OP_SH:
*PTR(VADDR(sim, ins), uint16_t) = sim->reg[ins.rt];
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break;
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case MIPS32R6_OP_SW:
*PTR(VADDR(sim, ins), uint32_t) = sim->reg[ins.rt];
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break;
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case MIPS32R6_OP_SLTI:
sim->reg[ins.rt] = (signed) sim->reg[ins.rs] <
(signed) SE(ins.immd) ? 1 : 0;
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break;
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case MIPS32R6_OP_SLTIU:
sim->reg[ins.rt] = sim->reg[ins.rs] < SE(ins.immd) ? 1 : 0;
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break;
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case MIPS32R6_OP_ORI:
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sim->reg[ins.rt] = sim->reg[ins.rs] | ins.immd;
break;
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case MIPS32R6_OP_XORI:
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sim->reg[ins.rt] = sim->reg[ins.rs] ^ ins.immd;
break;
default:
sim_dump(sim, "unknown op code (0b%05b)", ins.op);
}
}