mirror of
https://github.com/kenshineto/kern.git
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boot headers moved
This commit is contained in:
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commit
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GPG key ID:
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3 changed files with 255 additions and 258 deletions
boot/include
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@ -15,25 +15,25 @@
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/*
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** Video stuff
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*/
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#define VID_BASE_ADDR 0xB8000
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#define VID_BASE_ADDR 0xB8000
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/*
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** Memory management
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*/
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#define SEG_PRESENT 0x80
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#define SEG_PL_0 0x00
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#define SEG_PL_1 0x20
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#define SEG_PL_2 0x40
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#define SEG_PL_3 0x50
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#define SEG_SYSTEM 0x00
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#define SEG_NON_SYSTEM 0x10
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#define SEG_32BIT 0x04
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#define DESC_IGATE 0x06
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#define SEG_PRESENT 0x80
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#define SEG_PL_0 0x00
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#define SEG_PL_1 0x20
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#define SEG_PL_2 0x40
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#define SEG_PL_3 0x50
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#define SEG_SYSTEM 0x00
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#define SEG_NON_SYSTEM 0x10
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#define SEG_32BIT 0x04
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#define DESC_IGATE 0x06
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/*
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** Exceptions
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*/
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#define N_EXCEPTIONS 256
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#define N_EXCEPTIONS 256
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/*
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** Bit definitions in registers
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@ -45,91 +45,91 @@
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/*
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** EFLAGS
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*/
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#define EFL_RSVD 0xffc00000 /* reserved */
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#define EFL_MB0 0x00008020 /* must be zero */
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#define EFL_MB1 0x00000002 /* must be 1 */
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#define EFL_RSVD 0xffc00000 /* reserved */
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#define EFL_MB0 0x00008020 /* must be zero */
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#define EFL_MB1 0x00000002 /* must be 1 */
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#define EFL_ID 0x00200000
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#define EFL_VIP 0x00100000
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#define EFL_VIF 0x00080000
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#define EFL_AC 0x00040000
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#define EFL_VM 0x00020000
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#define EFL_RF 0x00010000
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#define EFL_NT 0x00004000
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#define EFL_ID 0x00200000
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#define EFL_VIP 0x00100000
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#define EFL_VIF 0x00080000
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#define EFL_AC 0x00040000
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#define EFL_VM 0x00020000
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#define EFL_RF 0x00010000
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#define EFL_NT 0x00004000
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#define EFL_IOPL 0x00003000
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#define EFL_OF 0x00000800
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#define EFL_DF 0x00000400
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#define EFL_IF 0x00000200
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#define EFL_TF 0x00000100
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#define EFL_SF 0x00000080
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#define EFL_ZF 0x00000040
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#define EFL_AF 0x00000010
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#define EFL_PF 0x00000004
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#define EFL_CF 0x00000001
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#define EFL_OF 0x00000800
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#define EFL_DF 0x00000400
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#define EFL_IF 0x00000200
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#define EFL_TF 0x00000100
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#define EFL_SF 0x00000080
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#define EFL_ZF 0x00000040
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#define EFL_AF 0x00000010
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#define EFL_PF 0x00000004
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#define EFL_CF 0x00000001
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/*
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** CR0, CR1, CR2, CR3, CR4
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**
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** IA-32 V3, page 2-12.
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*/
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#define CR0_RSVD 0x1ffaffc0
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#define CR0_PG 0x80000000
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#define CR0_CD 0x40000000
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#define CR0_NW 0x20000000
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#define CR0_AM 0x00040000
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#define CR0_WP 0x00010000
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#define CR0_NE 0x00000020
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#define CR0_ET 0x00000010
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#define CR0_TS 0x00000008
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#define CR0_EM 0x00000004
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#define CR0_MP 0x00000002
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#define CR0_PE 0x00000001
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#define CR0_RSVD 0x1ffaffc0
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#define CR0_PG 0x80000000
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#define CR0_CD 0x40000000
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#define CR0_NW 0x20000000
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#define CR0_AM 0x00040000
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#define CR0_WP 0x00010000
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#define CR0_NE 0x00000020
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#define CR0_ET 0x00000010
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#define CR0_TS 0x00000008
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#define CR0_EM 0x00000004
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#define CR0_MP 0x00000002
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#define CR0_PE 0x00000001
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#define CR1_RSVD 0xffffffff
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#define CR1_RSVD 0xffffffff
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#define CR2_RSVD 0x00000000
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#define CR2_RSVD 0x00000000
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#define CR2_PF_LIN_ADDR 0xffffffff
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#define CR3_RSVD 0x00000fe7
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#define CR3_PD_BASE 0xfffff000
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#define CR3_PCD 0x00000010
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#define CR3_PWT 0x00000008
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#define CR3_RSVD 0x00000fe7
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#define CR3_PD_BASE 0xfffff000
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#define CR3_PCD 0x00000010
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#define CR3_PWT 0x00000008
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#define CR4_RSVD 0xfd001000
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#define CR4_UINT 0x02000000
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#define CR4_PKS 0x01000000
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#define CR4_CET 0x00800000
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#define CR4_PKE 0x00400000
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#define CR4_SMAP 0x00200000
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#define CR4_SMEP 0x00100000
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#define CR4_KL 0x00080000
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#define CR4_OSXS 0x00040000
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#define CR4_PCID 0x00020000
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#define CR4_FSGS 0x00010000
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#define CR4_SMXE 0x00004000
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#define CR4_VMXE 0x00002000
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#define CR4_LA57 0x00001000
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#define CR4_UMIP 0x00000800
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#define CR4_OSXMMEXCPT 0x00000400
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#define CR4_OSFXSR 0x00000200
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#define CR4_PCE 0x00000100
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#define CR4_PGE 0x00000080
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#define CR4_MCE 0x00000040
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#define CR4_PAE 0x00000020
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#define CR4_PSE 0x00000010
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#define CR4_DE 0x00000008
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#define CR4_TSD 0x00000004
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#define CR4_PVI 0x00000002
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#define CR4_VME 0x00000001
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#define CR4_RSVD 0xfd001000
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#define CR4_UINT 0x02000000
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#define CR4_PKS 0x01000000
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#define CR4_CET 0x00800000
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#define CR4_PKE 0x00400000
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#define CR4_SMAP 0x00200000
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#define CR4_SMEP 0x00100000
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#define CR4_KL 0x00080000
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#define CR4_OSXS 0x00040000
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#define CR4_PCID 0x00020000
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#define CR4_FSGS 0x00010000
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#define CR4_SMXE 0x00004000
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#define CR4_VMXE 0x00002000
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#define CR4_LA57 0x00001000
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#define CR4_UMIP 0x00000800
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#define CR4_OSXMMEXCPT 0x00000400
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#define CR4_OSFXSR 0x00000200
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#define CR4_PCE 0x00000100
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#define CR4_PGE 0x00000080
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#define CR4_MCE 0x00000040
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#define CR4_PAE 0x00000020
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#define CR4_PSE 0x00000010
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#define CR4_DE 0x00000008
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#define CR4_TSD 0x00000004
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#define CR4_PVI 0x00000002
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#define CR4_VME 0x00000001
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/*
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** PMode segment selector field masks
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**
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** IA-32 V3, page 3-8.
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*/
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#define SEG_SEL_IX_MASK 0xfff8
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#define SEG_SEL_TI_MASK 0x0004
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#define SEG_SEL_RPL_MASK 0x0003
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#define SEG_SEL_IX_MASK 0xfff8
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#define SEG_SEL_TI_MASK 0x0004
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#define SEG_SEL_RPL_MASK 0x0003
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/*
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** Segment descriptor bytes
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@ -150,43 +150,43 @@
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** 4: system/user
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** 3-0: type
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*/
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#define SEG_ACCESS_P_MASK 0x80
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# define SEG_PRESENT 0x80
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# define SEG_NOT_PRESENT 0x00
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#define SEG_ACCESS_P_MASK 0x80
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#define SEG_PRESENT 0x80
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#define SEG_NOT_PRESENT 0x00
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#define SEG_ACCESS_DPL_MASK 0x60
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# define SEG_DPL_0 0x00
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# define SEG_DPL_1 0x20
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# define SEG_DPL_2 0x40
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# define SEG_DPL_3 0x60
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#define SEG_ACCESS_DPL_MASK 0x60
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#define SEG_DPL_0 0x00
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#define SEG_DPL_1 0x20
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#define SEG_DPL_2 0x40
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#define SEG_DPL_3 0x60
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#define SEG_ACCESS_S_MASK 0x10
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# define SEG_SYSTEM 0x00
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# define SEG_NON_SYSTEM 0x10
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#define SEG_ACCESS_S_MASK 0x10
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#define SEG_SYSTEM 0x00
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#define SEG_NON_SYSTEM 0x10
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#define SEG_TYPE_MASK 0x0f
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# define SEG_DATA_A_BIT 0x1
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# define SEG_DATA_W_BIT 0x2
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# define SEG_DATA_E_BIT 0x4
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# define SEG_CODE_A_BIT 0x1
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# define SEG_CODE_R_BIT 0x2
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# define SEG_CODE_C_BIT 0x4
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# define SEG_DATA_RO 0x0
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# define SEG_DATA_ROA 0x1
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# define SEG_DATA_RW 0x2
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# define SEG_DATA_RWA 0x3
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# define SEG_DATA_RO_XD 0x4
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# define SEG_DATA_RO_XDA 0x5
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# define SEG_DATA_RW_XW 0x6
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# define SEG_DATA_RW_XWA 0x7
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# define SEG_CODE_XO 0x8
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# define SEG_CODE_XOA 0x9
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# define SEG_CODE_XR 0xa
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# define SEG_CODE_XRA 0xb
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# define SEG_CODE_XO_C 0xc
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# define SEG_CODE_XO_CA 0xd
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# define SEG_CODE_XR_C 0xe
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# define SEG_CODE_XR_CA 0xf
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#define SEG_TYPE_MASK 0x0f
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#define SEG_DATA_A_BIT 0x1
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#define SEG_DATA_W_BIT 0x2
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#define SEG_DATA_E_BIT 0x4
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#define SEG_CODE_A_BIT 0x1
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#define SEG_CODE_R_BIT 0x2
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#define SEG_CODE_C_BIT 0x4
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#define SEG_DATA_RO 0x0
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#define SEG_DATA_ROA 0x1
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#define SEG_DATA_RW 0x2
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#define SEG_DATA_RWA 0x3
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#define SEG_DATA_RO_XD 0x4
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#define SEG_DATA_RO_XDA 0x5
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#define SEG_DATA_RW_XW 0x6
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#define SEG_DATA_RW_XWA 0x7
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#define SEG_CODE_XO 0x8
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#define SEG_CODE_XOA 0x9
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#define SEG_CODE_XR 0xa
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#define SEG_CODE_XRA 0xb
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#define SEG_CODE_XO_C 0xc
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#define SEG_CODE_XO_CA 0xd
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#define SEG_CODE_XR_C 0xe
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#define SEG_CODE_XR_CA 0xf
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/*
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** Byte 6: sizes
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@ -197,48 +197,47 @@
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** 3-0: upper 4 bits of limit
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** 7: base address 31:24
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*/
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#define SEG_SIZE_G_MASK 0x80
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# define SEG_GRAN_BYTE 0x00
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# define SEG_GRAN_4KBYTE 0x80
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#define SEG_SIZE_G_MASK 0x80
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#define SEG_GRAN_BYTE 0x00
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#define SEG_GRAN_4KBYTE 0x80
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#define SEG_SIZE_D_B_MASK 0x40
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# define SEG_DB_16BIT 0x00
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# define SEG_DB_32BIT 0x40
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#define SEG_SIZE_D_B_MASK 0x40
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#define SEG_DB_16BIT 0x00
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#define SEG_DB_32BIT 0x40
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#define SEG_SIZE_L_MASK 0x20
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# define SEG_L_64BIT 0x20
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# define SEG_L_32BIT 0x00
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#define SEG_SIZE_L_MASK 0x20
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#define SEG_L_64BIT 0x20
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#define SEG_L_32BIT 0x00
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#define SEG_SIZE_AVL_MASK 0x10
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#define SEG_SIZE_AVL_MASK 0x10
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#define SEG_SIZE_LIM_19_16_MASK 0x0f
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/*
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** System-segment and gate-descriptor types
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**
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** IA-32 V3, page 3-15.
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*/
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// type 0: reserved
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// type 0: reserved
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#define SEG_SYS_16BIT_TSS_AVAIL 0x1
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#define SEG_SYS_LDT 0x2
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#define SEG_SYS_16BIT_TSS_BUSY 0x3
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#define SEG_SYS_LDT 0x2
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#define SEG_SYS_16BIT_TSS_BUSY 0x3
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#define SEG_SYS_16BIT_CALL_GATE 0x4
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#define SEG_SYS_TASK_GATE 0x5
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#define SEG_SYS_16BIT_INT_GATE 0x6
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#define SEG_SYS_TASK_GATE 0x5
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#define SEG_SYS_16BIT_INT_GATE 0x6
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#define SEG_SYS_16BIT_TRAP_GATE 0x7
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// type 8: reserved
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// type 8: reserved
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#define SEG_SYS_32BIT_TSS_AVAIL 0x9
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// type A: reserved
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#define SEG_SYS_32BIT_TSS_BUSY 0xb
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// type A: reserved
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#define SEG_SYS_32BIT_TSS_BUSY 0xb
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#define SEG_SYS_32BIT_CALL_GATE 0xc
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// type D: reserved
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#define SEG_SYS_32BIT_INT_GATE 0xe
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// type D: reserved
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#define SEG_SYS_32BIT_INT_GATE 0xe
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#define SEG_SYS_32BIT_TRAP_GATE 0xf
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/*
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** IDT Descriptors
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**
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**
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** IA-32 V3, page 5-13.
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**
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** All have a segment selector in bytes 2 and 3; Task Gate descriptors
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@ -246,58 +245,58 @@
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** and 7 devoted to the 16 bits of the Offset, with the low nybble of
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** byte 4 reserved.
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*/
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#define IDT_PRESENT 0x8000
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#define IDT_DPL_MASK 0x6000
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# define IDT_DPL_0 0x0000
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# define IDT_DPL_1 0x2000
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# define IDT_DPL_2 0x4000
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# define IDT_DPL_3 0x6000
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#define IDT_GATE_TYPE 0x0f00
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# define IDT_TASK_GATE 0x0500
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# define IDT_INT16_GATE 0x0600
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# define IDT_INT32_GATE 0x0e00
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# define IDT_TRAP16_GATE 0x0700
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# define IDT_TRAP32_GATE 0x0f00
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#define IDT_PRESENT 0x8000
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#define IDT_DPL_MASK 0x6000
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#define IDT_DPL_0 0x0000
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#define IDT_DPL_1 0x2000
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#define IDT_DPL_2 0x4000
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#define IDT_DPL_3 0x6000
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#define IDT_GATE_TYPE 0x0f00
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#define IDT_TASK_GATE 0x0500
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#define IDT_INT16_GATE 0x0600
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#define IDT_INT32_GATE 0x0e00
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#define IDT_TRAP16_GATE 0x0700
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#define IDT_TRAP32_GATE 0x0f00
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/*
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** Interrupt vectors
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*/
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// predefined by the architecture
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#define VEC_DIVIDE_ERROR 0x00
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#define VEC_DEBUG_EXCEPTION 0x01
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#define VEC_NMI_INTERRUPT 0x02
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#define VEC_BREAKPOINT 0x03
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#define VEC_OVERFLOW 0x04
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#define VEC_BOUND_RANGE_EXCEEDED 0x05
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#define VEC_INVALID_OPCODE 0x06
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#define VEC_DEVICE_NOT_AVAILABLE 0x07
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#define VEC_DOUBLE_FAULT 0x08
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#define VEC_COPROCESSOR_OVERRUN 0x09
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#define VEC_INVALID_TSS 0x0a
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#define VEC_SEGMENT_NOT_PRESENT 0x0b
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#define VEC_STACK_FAULT 0x0c
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#define VEC_GENERAL_PROTECTION 0x0d
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#define VEC_PAGE_FAULT 0x0e
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#define VEC_DIVIDE_ERROR 0x00
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#define VEC_DEBUG_EXCEPTION 0x01
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#define VEC_NMI_INTERRUPT 0x02
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#define VEC_BREAKPOINT 0x03
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#define VEC_OVERFLOW 0x04
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#define VEC_BOUND_RANGE_EXCEEDED 0x05
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#define VEC_INVALID_OPCODE 0x06
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#define VEC_DEVICE_NOT_AVAILABLE 0x07
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#define VEC_DOUBLE_FAULT 0x08
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#define VEC_COPROCESSOR_OVERRUN 0x09
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#define VEC_INVALID_TSS 0x0a
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#define VEC_SEGMENT_NOT_PRESENT 0x0b
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#define VEC_STACK_FAULT 0x0c
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#define VEC_GENERAL_PROTECTION 0x0d
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#define VEC_PAGE_FAULT 0x0e
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// 0x0f is reserved - unused
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#define VEC_FPU_ERROR 0x10
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#define VEC_ALIGNMENT_CHECK 0x11
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#define VEC_MACHINE_CHECK 0x12
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#define VEC_SIMD_FP_EXCEPTION 0x13
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#define VEC_VIRT_EXCEPTION 0x14
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#define VEC_CTRL_PROT_EXCEPTION 0x15
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#define VEC_FPU_ERROR 0x10
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#define VEC_ALIGNMENT_CHECK 0x11
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#define VEC_MACHINE_CHECK 0x12
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#define VEC_SIMD_FP_EXCEPTION 0x13
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#define VEC_VIRT_EXCEPTION 0x14
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#define VEC_CTRL_PROT_EXCEPTION 0x15
|
||||
// 0x16 through 0x1f are reserved
|
||||
|
||||
// 0x20 through 0xff are user-defined, non-reserved
|
||||
|
||||
// IRQ0 through IRQ15 will use vectors 0x20 through 0x2f
|
||||
#define VEC_TIMER 0x20
|
||||
#define VEC_KBD 0x21
|
||||
#define VEC_COM2 0x23
|
||||
#define VEC_COM1 0x24
|
||||
#define VEC_PARALLEL 0x25
|
||||
#define VEC_FLOPPY 0x26
|
||||
#define VEC_MYSTERY 0x27
|
||||
#define VEC_MOUSE 0x2c
|
||||
#define VEC_TIMER 0x20
|
||||
#define VEC_KBD 0x21
|
||||
#define VEC_COM2 0x23
|
||||
#define VEC_COM1 0x24
|
||||
#define VEC_PARALLEL 0x25
|
||||
#define VEC_FLOPPY 0x26
|
||||
#define VEC_MYSTERY 0x27
|
||||
#define VEC_MOUSE 0x2c
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -13,61 +13,61 @@
|
|||
** BIOS-related memory addresses
|
||||
*/
|
||||
|
||||
#define BIOS_BDA 0x0400
|
||||
#define BIOS_BDA 0x0400
|
||||
|
||||
/*
|
||||
** Selected BIOS interrupt numbers
|
||||
*/
|
||||
|
||||
#define BIOS_TIMER 0x08
|
||||
#define BIOS_KBD 0x09
|
||||
#define BIOS_VIDEO 0x10
|
||||
#define BIOS_EQUIP 0x11
|
||||
#define BIOS_MSIZ 0x12
|
||||
#define BIOS_DISK 0x13
|
||||
#define BIOS_SERIAL 0x14
|
||||
#define BIOS_MISC 0x15
|
||||
#define BIOS_KBDSVC 0x16
|
||||
#define BIOS_PRTSVC 0x17
|
||||
#define BIOS_BOOT 0x19
|
||||
#define BIOS_RTCPCI 0x1a
|
||||
#define BIOS_TIMER 0x08
|
||||
#define BIOS_KBD 0x09
|
||||
#define BIOS_VIDEO 0x10
|
||||
#define BIOS_EQUIP 0x11
|
||||
#define BIOS_MSIZ 0x12
|
||||
#define BIOS_DISK 0x13
|
||||
#define BIOS_SERIAL 0x14
|
||||
#define BIOS_MISC 0x15
|
||||
#define BIOS_KBDSVC 0x16
|
||||
#define BIOS_PRTSVC 0x17
|
||||
#define BIOS_BOOT 0x19
|
||||
#define BIOS_RTCPCI 0x1a
|
||||
|
||||
// BIOS video commands (AH)
|
||||
#define BV_W_ADV 0x0e
|
||||
#define BV_W_ADV 0x0e
|
||||
|
||||
// BIOS disk commands (AH)
|
||||
#define BD_RESET 0x00
|
||||
#define BD_CHECK 0x01
|
||||
#define BD_RDSECT 0x02
|
||||
#define BD_WRSECT 0x03
|
||||
#define BD_PARAMS 0x08
|
||||
#define BD_RESET 0x00
|
||||
#define BD_CHECK 0x01
|
||||
#define BD_RDSECT 0x02
|
||||
#define BD_WRSECT 0x03
|
||||
#define BD_PARAMS 0x08
|
||||
|
||||
// BIOS disk commands with parameters (AX)
|
||||
#define BD_READ(n) ((BD_RDSECT << 8) | (n))
|
||||
#define BD_READ1 0x0201
|
||||
#define BD_READ(n) ((BD_RDSECT << 8) | (n))
|
||||
#define BD_READ1 0x0201
|
||||
|
||||
// CMOS ports (used for masking NMIs)
|
||||
#define CMOS_ADDR 0x70
|
||||
#define CMOS_DATA 0x71
|
||||
#define CMOS_ADDR 0x70
|
||||
#define CMOS_DATA 0x71
|
||||
|
||||
// important related commands
|
||||
#define NMI_ENABLE 0x00
|
||||
#define NMI_DISABLE 0x80
|
||||
#define NMI_ENABLE 0x00
|
||||
#define NMI_DISABLE 0x80
|
||||
|
||||
/*
|
||||
** Physical Memory Map Table (0000:2D00 - 0000:7c00)
|
||||
**
|
||||
** Primarily used with the BIOS_MISC interrupt
|
||||
*/
|
||||
#define MMAP_SEG 0x02D0
|
||||
#define MMAP_DISP 0x0000
|
||||
#define MMAP_ADDR ((MMAP_SEG << 4) + MMAP_DISP)
|
||||
#define MMAP_SECTORS 0x0a
|
||||
#define MMAP_SEG 0x02D0
|
||||
#define MMAP_DISP 0x0000
|
||||
#define MMAP_ADDR ((MMAP_SEG << 4) + MMAP_DISP)
|
||||
#define MMAP_SECTORS 0x0a
|
||||
|
||||
#define MMAP_ENT 24 /* bytes per entry */
|
||||
#define MMAP_MAX_ENTS (BOOT_ADDR - MMAP_ADDR - 4) / 24
|
||||
#define MMAP_ENT 24 /* bytes per entry */
|
||||
#define MMAP_MAX_ENTS (BOOT_ADDR - MMAP_ADDR - 4) / 24
|
||||
|
||||
#define MMAP_CODE 0xE820 /* int 0x15 code */
|
||||
#define MMAP_MAGIC_NUM 0x534D4150 /* for 0xE820 interrupt */
|
||||
#define MMAP_CODE 0xE820 /* int 0x15 code */
|
||||
#define MMAP_MAGIC_NUM 0x534D4150 /* for 0xE820 interrupt */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,86 +9,85 @@
|
|||
** Addresses where various stuff goes in memory.
|
||||
*/
|
||||
|
||||
#ifndef BOOTSTRAP_H_
|
||||
#define BOOTSTRAP_H_
|
||||
#ifndef BOOTSTRAP_H_
|
||||
#define BOOTSTRAP_H_
|
||||
|
||||
/*
|
||||
** The boot device
|
||||
*/
|
||||
#define BDEV_FLOPPY 0x00
|
||||
#define BDEV_USB 0x80 /* hard drive */
|
||||
#define BDEV_FLOPPY 0x00
|
||||
#define BDEV_USB 0x80 /* hard drive */
|
||||
|
||||
#define BDEV BDEV_USB /* default */
|
||||
#define BDEV BDEV_USB /* default */
|
||||
|
||||
/*
|
||||
** Bootstrap definitions
|
||||
*/
|
||||
#define BOOT_SEG 0x07c0 /* 07c0:0000 */
|
||||
#define BOOT_DISP 0x0000
|
||||
#define BOOT_ADDR (BOOT_SEG << 4 + BOOT_DISP)
|
||||
#define BOOT_SEG 0x07c0 /* 07c0:0000 */
|
||||
#define BOOT_DISP 0x0000
|
||||
#define BOOT_ADDR (BOOT_SEG << 4 + BOOT_DISP)
|
||||
|
||||
#define PART2_DISP 0x0200 /* 07c0:0200 */
|
||||
#define PART2_ADDR (BOOT_SEG << 4 + PART2_DISP)
|
||||
#define PART2_DISP 0x0200 /* 07c0:0200 */
|
||||
#define PART2_ADDR (BOOT_SEG << 4 + PART2_DISP)
|
||||
|
||||
#define SECTOR_SIZE 0x200 /* 512 bytes */
|
||||
#define SECTOR_SIZE 0x200 /* 512 bytes */
|
||||
|
||||
/* Note: this assumes the bootstrap is two sectors long! */
|
||||
#define BOOT_SIZE (SECTOR_SIZE + SECTOR_SIZE)
|
||||
#define BOOT_SIZE (SECTOR_SIZE + SECTOR_SIZE)
|
||||
|
||||
#define OFFSET_LIMIT (0x10000 - SECTOR_SIZE)
|
||||
#define OFFSET_LIMIT (0x10000 - SECTOR_SIZE)
|
||||
|
||||
#define BOOT_SP_DISP 0x4000 /* stack pointer 07c0:4000, or 0xbc00 */
|
||||
#define BOOT_SP_ADDR (BOOT_SEG << 4 + BOOT_SP_DISP)
|
||||
|
||||
#define SECTOR1_END (BOOT_ADDR + SECTOR_SIZE)
|
||||
#define SECTOR2_END (BOOT_ADDR + BOOT_SIZE)
|
||||
#define BOOT_SP_DISP 0x4000 /* stack pointer 07c0:4000, or 0xbc00 */
|
||||
#define BOOT_SP_ADDR (BOOT_SEG << 4 + BOOT_SP_DISP)
|
||||
|
||||
#define SECTOR1_END (BOOT_ADDR + SECTOR_SIZE)
|
||||
#define SECTOR2_END (BOOT_ADDR + BOOT_SIZE)
|
||||
|
||||
/*
|
||||
** The target program itself
|
||||
*/
|
||||
#define TARGET_SEG 0x00001000 /* 1000:0000 */
|
||||
#define TARGET_ADDR 0x00010000 /* and upward */
|
||||
#define TARGET_STACK 0x00010000 /* and downward */
|
||||
#define TARGET_SEG 0x00001000 /* 1000:0000 */
|
||||
#define TARGET_ADDR 0x00010000 /* and upward */
|
||||
#define TARGET_STACK 0x00010000 /* and downward */
|
||||
|
||||
/*
|
||||
** The Global Descriptor Table (0000:0500 - 0000:2500)
|
||||
*/
|
||||
#define GDT_SEG 0x00000050
|
||||
#define GDT_ADDR 0x00000500
|
||||
#define GDT_SEG 0x00000050
|
||||
#define GDT_ADDR 0x00000500
|
||||
|
||||
/* segment register values */
|
||||
#define GDT_LINEAR 0x0008 /* All of memory, R/W */
|
||||
#define GDT_CODE 0x0010 /* All of memory, R/E */
|
||||
#define GDT_DATA 0x0018 /* All of memory, R/W */
|
||||
#define GDT_STACK 0x0020 /* All of memory, R/W */
|
||||
/* segment register values */
|
||||
#define GDT_LINEAR 0x0008 /* All of memory, R/W */
|
||||
#define GDT_CODE 0x0010 /* All of memory, R/E */
|
||||
#define GDT_DATA 0x0018 /* All of memory, R/W */
|
||||
#define GDT_STACK 0x0020 /* All of memory, R/W */
|
||||
|
||||
/*
|
||||
** The Interrupt Descriptor Table (0000:2500 - 0000:2D00)
|
||||
*/
|
||||
#define IDT_SEG 0x00000250
|
||||
#define IDT_ADDR 0x00002500
|
||||
#define IDT_SEG 0x00000250
|
||||
#define IDT_ADDR 0x00002500
|
||||
|
||||
/*
|
||||
** Additional I/O ports used by the bootstrap code
|
||||
*/
|
||||
|
||||
// keyboard controller
|
||||
#define KBD_DATA 0x60
|
||||
#define KBD_CMD 0x64
|
||||
#define KBD_STAT 0x64
|
||||
#define KBD_DATA 0x60
|
||||
#define KBD_CMD 0x64
|
||||
#define KBD_STAT 0x64
|
||||
|
||||
// status register bits
|
||||
#define KBD_OBSTAT 0x01
|
||||
#define KBD_IBSTAT 0x02
|
||||
#define KBD_SYSFLAG 0x04
|
||||
#define KBD_CMDDAT 0x08
|
||||
#define KBD_OBSTAT 0x01
|
||||
#define KBD_IBSTAT 0x02
|
||||
#define KBD_SYSFLAG 0x04
|
||||
#define KBD_CMDDAT 0x08
|
||||
|
||||
// commands
|
||||
#define KBD_P1_DISABLE 0xad
|
||||
#define KBD_P1_ENABLE 0xae
|
||||
#define KBD_RD_OPORT 0xd0
|
||||
#define KBD_WT_OPORT 0xd1
|
||||
#define KBD_P1_DISABLE 0xad
|
||||
#define KBD_P1_ENABLE 0xae
|
||||
#define KBD_RD_OPORT 0xd0
|
||||
#define KBD_WT_OPORT 0xd1
|
||||
|
||||
#ifdef ASM_SRC
|
||||
|
||||
|
|
@ -101,17 +100,16 @@
|
|||
// .byte granularity byte
|
||||
// .byte upper 8 bits of base
|
||||
// we use 4K units, so we ignore the lower 12 bits of the limit
|
||||
#define SEGNULL \
|
||||
.word 0, 0, 0, 0
|
||||
#define SEGNULL .word 0, 0, 0, 0
|
||||
|
||||
#define SEGMENT(base,limit,dpl,type) \
|
||||
.word (((limit) >> 12) & 0xffff); \
|
||||
.word ((base) & 0xffff) ; \
|
||||
.byte (((base) >> 16) & 0xff) ; \
|
||||
.byte (SEG_PRESENT | (dpl) | SEG_NON_SYSTEM | (type)) ; \
|
||||
.byte (SEG_GRAN_4KBYTE | SEG_DB_32BIT | (((limit) >> 28) & 0xf)) ; \
|
||||
.byte (((base) >> 24) & 0xff)
|
||||
#define SEGMENT(base, limit, dpl, type) \
|
||||
.word(((limit) >> 12) & 0xffff); \
|
||||
.word((base) & 0xffff); \
|
||||
.byte(((base) >> 16) & 0xff); \
|
||||
.byte(SEG_PRESENT | (dpl) | SEG_NON_SYSTEM | (type)); \
|
||||
.byte(SEG_GRAN_4KBYTE | SEG_DB_32BIT | (((limit) >> 28) & 0xf)); \
|
||||
.byte(((base) >> 24) & 0xff)
|
||||
|
||||
#endif /* ASM_SRC */
|
||||
#endif /* ASM_SRC */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue