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-rw-r--r--src/arch/x86_common/acpi.c13
-rw-r--r--src/arch/x86_common/drivers/bochs.c72
-rw-r--r--src/arch/x86_common/drivers/pci.c57
-rw-r--r--src/arch/x86_common/drivers/pic.c89
-rw-r--r--src/arch/x86_common/drivers/serial.c47
-rw-r--r--src/arch/x86_common/include/bindings.h53
-rw-r--r--src/arch/x86_common/include/mboot.h11
-rw-r--r--src/arch/x86_common/include/pic.h31
-rw-r--r--src/arch/x86_common/mboot.c283
9 files changed, 656 insertions, 0 deletions
diff --git a/src/arch/x86_common/acpi.c b/src/arch/x86_common/acpi.c
new file mode 100644
index 0000000..2392185
--- /dev/null
+++ b/src/arch/x86_common/acpi.c
@@ -0,0 +1,13 @@
+#include <bindings.h>
+
+#define ACPI_INTERNAL
+#include <sys/acpi.h>
+
+void acpi_sys_enable(struct acpi_state *state) {
+ outb(state->fadt->smi_command_port, state->fadt->acpi_enable);
+}
+
+int acpi_sys_shutdown(struct acpi_state *state) {
+ outw((unsigned int) state->fadt->pm1_a_control_block, state->SLP_TYPb | state->SLP_EN);
+ return -1;
+}
diff --git a/src/arch/x86_common/drivers/bochs.c b/src/arch/x86_common/drivers/bochs.c
new file mode 100644
index 0000000..8e9ca2b
--- /dev/null
+++ b/src/arch/x86_common/drivers/bochs.c
@@ -0,0 +1,72 @@
+#include <lib.h>
+#include <memory.h>
+#include <stdint.h>
+#include <panic.h>
+#include <pci.h>
+#include <bochs.h>
+#include <bindings.h>
+
+#define INDEX 0x1CE
+#define DATA 0x1CF
+
+#define INDEX_ID 0
+#define INDEX_XRES 1
+#define INDEX_YRES 2
+#define INDEX_BPP 3
+#define INDEX_ENABLE 4
+#define INDEX_BANK 5
+#define INDEX_VIRT_WIDTH 6
+#define INDEX_VIRT_HEIGHT 7
+#define INDEX_X_OFFSET 8
+#define INDEX_Y_OFFSET 9
+
+#define DATA_DISP_DISABLE 0x00
+#define DATA_DISP_ENABLE 0x01
+#define DATA_LFB_ENABLE 0x40
+#define DATA_NO_CLEAR_MEM 0x80
+
+#define BOCHS_PCI_VENDOR 0x1234
+#define BOCHS_PCI_DEVICE 0x1111
+
+static void write(uint16_t index, uint16_t data) {
+ outw(INDEX, index);
+ outw(DATA, data);
+}
+
+static uint16_t read(uint16_t value) {
+ outw(INDEX, value);
+ return inw(DATA);
+}
+
+static int is_available(void) {
+ return (read(INDEX_ID) == 0xB0C5);
+}
+
+static void set_mode(uint16_t width, uint16_t height, uint16_t bit_depth, int lfb, int clear) {
+ write(INDEX_ENABLE, DATA_DISP_DISABLE);
+ write(INDEX_XRES, width);
+ write(INDEX_YRES, height);
+ write(INDEX_BPP, bit_depth);
+ write(INDEX_ENABLE, DATA_DISP_ENABLE |
+ (lfb ? DATA_LFB_ENABLE : 0) |
+ (clear ? 0 : DATA_NO_CLEAR_MEM));
+}
+
+volatile uint32_t *bochs_init(uint16_t width, uint16_t height, uint8_t bit_depth) {
+
+ set_mode(width, height, bit_depth, true, true);
+
+ if (!is_available())
+ return NULL;
+
+ struct pci_device bochs = {0};
+ bool found = pci_findby_id(&bochs, BOCHS_PCI_DEVICE, BOCHS_PCI_VENDOR, NULL);
+ if (!found)
+ return NULL;
+
+ uint32_t bar0 = pci_rcfg_d(bochs, PCI_BAR0_D);
+ uint32_t *addr = (uint32_t *) (uintptr_t) bar0;
+ addr = mmap(addr, width * height * bit_depth);
+
+ return addr;
+}
diff --git a/src/arch/x86_common/drivers/pci.c b/src/arch/x86_common/drivers/pci.c
new file mode 100644
index 0000000..579562a
--- /dev/null
+++ b/src/arch/x86_common/drivers/pci.c
@@ -0,0 +1,57 @@
+#include <pci.h>
+#include <bindings.h>
+
+#define PCI_INTERNAL
+#include <sys/pci.h>
+
+#define CONF_ADDR 0xCF8
+#define CONF_DATA 0xCFC
+
+uint32_t pci_sys_rcfg_d(struct pci_device dev, uint8_t offset) {
+ uint32_t addr = 0x80000000;
+ addr |= ((uint32_t)dev.bus) << 16;
+ addr |= ((uint32_t)dev.device) << 11;
+ addr |= ((uint32_t)dev.function) << 8;
+ addr |= offset & 0xFC;
+
+ outl(CONF_ADDR, addr);
+ uint32_t in = inl(CONF_DATA);
+ return in;
+}
+
+uint16_t pci_sys_rcfg_w(struct pci_device dev, uint8_t offset) {
+ uint32_t dword = pci_sys_rcfg_d(dev, offset);
+ return (uint16_t)((dword >> ((offset & 2) * 8)) & 0xFFFF);
+}
+
+uint8_t pci_sys_rcfg_b(struct pci_device dev, uint8_t offset) {
+ uint32_t dword = pci_sys_rcfg_d(dev, offset);
+ return (uint8_t)((dword >> ((offset & 3) * 8)) & 0xFF);
+}
+
+void pci_sys_wcfg_d(struct pci_device dev, uint8_t offset, uint32_t dword) {
+ uint32_t addr = 0x80000000;
+ addr |= ((uint32_t)dev.bus) << 16;
+ addr |= ((uint32_t)dev.device) << 11;
+ addr |= ((uint32_t)dev.function) << 8;
+ addr |= offset & 0xFC;
+
+ outl(CONF_ADDR, addr);
+ outl(CONF_DATA, dword);
+}
+
+void pci_sys_wcfg_w(struct pci_device dev, uint8_t offset, uint16_t word) {
+ size_t shift = (offset & 2) * 8;
+ uint32_t dword = pci_sys_rcfg_d(dev, offset);
+ dword &= ~(0xFFFF << shift);
+ dword |= word << shift;
+ pci_sys_wcfg_d(dev, offset, dword);
+}
+
+void pci_sys_wcfg_b(struct pci_device dev, uint8_t offset, uint8_t byte) {
+ size_t shift = (offset & 3) * 8;
+ uint32_t dword = pci_sys_rcfg_d(dev, offset);
+ dword &= ~(0xFF << shift);
+ dword |= byte << shift;
+ pci_sys_wcfg_d(dev, offset, dword);
+}
diff --git a/src/arch/x86_common/drivers/pic.c b/src/arch/x86_common/drivers/pic.c
new file mode 100644
index 0000000..d911648
--- /dev/null
+++ b/src/arch/x86_common/drivers/pic.c
@@ -0,0 +1,89 @@
+#include <bindings.h>
+#include <pic.h>
+
+#define PIC1 0x20 /* IO base address for master PIC */
+#define PIC2 0xA0 /* IO base address for slave PIC */
+#define PIC1_COMMAND PIC1
+#define PIC1_DATA (PIC1+1)
+#define PIC2_COMMAND PIC2
+#define PIC2_DATA (PIC2+1)
+
+#define PIC_EOI 0x20 /* End-of-interrupt command code */
+
+#define ICW1_ICW4 0x01 /* Indicates that ICW4 will be present */
+#define ICW1_SINGLE 0x02 /* Single (cascade) mode */
+#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */
+#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
+#define ICW1_INIT 0x10 /* Initialization - required! */
+
+#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
+#define ICW4_AUTO 0x02 /* Auto (normal) EOI */
+#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
+#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
+#define ICW4_SFNM 0x10 /* Special fully nested (not) */
+
+void pic_remap(void) {
+ uint8_t a1, a2;
+
+ a1 = inb(PIC1_DATA); // save masks
+ a2 = inb(PIC2_DATA);
+
+ outb(PIC1_COMMAND, ICW1_INIT | ICW1_ICW4); // starts the initialization sequence (in cascade mode)
+ io_wait();
+ outb(PIC2_COMMAND, ICW1_INIT | ICW1_ICW4);
+ io_wait();
+ outb(PIC1_DATA, PIC_REMAP_OFFSET); // ICW2: Master PIC vector offset
+ io_wait();
+ outb(PIC2_DATA, PIC_REMAP_OFFSET + 8); // ICW2: Slave PIC vector offset
+ io_wait();
+ outb(PIC1_DATA, 4); // ICW3: tell Master PIC that there is a slave PIC at IRQ2 (0000 0100)
+ io_wait();
+ outb(PIC2_DATA, 2); // ICW3: tell Slave PIC its cascade identity (0000 0010)
+ io_wait();
+
+ outb(PIC1_DATA, ICW4_8086); // ICW4: have the PICs use 8086 mode (and not 8080 mode)
+ io_wait();
+ outb(PIC2_DATA, ICW4_8086);
+ io_wait();
+
+ outb(PIC1_DATA, a1); // restore saved masks.
+ outb(PIC2_DATA, a2);
+}
+
+void pic_mask(int irq) {
+ uint16_t port;
+ uint8_t mask;
+ if (irq < 8) {
+ port = PIC1_DATA;
+ } else {
+ port = PIC2_DATA;
+ irq -= 8;
+ }
+ mask = inb(port) | (1 << irq);
+ outb(port, mask);
+}
+
+void pic_unmask(int irq) {
+ uint16_t port;
+ uint8_t mask;
+ if (irq < 8) {
+ port = PIC1_DATA;
+ } else {
+ irq -= 8;
+ port = PIC2_DATA;
+ }
+ mask = inb(port) & ~(1 << irq);
+ outb(port, mask);
+}
+
+void pic_disable(void) {
+ outb(PIC1_DATA, 0xff);
+ outb(PIC2_DATA, 0xff);
+}
+
+void pic_eoi(int irq) {
+ if (irq >= 8) {
+ outb(PIC2_COMMAND, PIC_EOI);
+ }
+ outb(PIC1_COMMAND, PIC_EOI);
+}
diff --git a/src/arch/x86_common/drivers/serial.c b/src/arch/x86_common/drivers/serial.c
new file mode 100644
index 0000000..255f8fc
--- /dev/null
+++ b/src/arch/x86_common/drivers/serial.c
@@ -0,0 +1,47 @@
+#include <serial.h>
+#include <bindings.h>
+
+#define PORT 0x3F8
+
+// initialize the specified COM port for serial
+// see https://wiki.osdev.org/Serial_Ports
+// and https://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming
+int serial_init(void) {
+ outb(PORT + 1, 0x00); // disable interrupts
+ outb(PORT + 3, 0x80); // enable DLAB (divisor latch access bit)
+ outb(PORT + 0, 0x03); // (lo) Set baud divisor to 3 38400 baud
+ outb(PORT + 1, 0x00); // (hi)
+ outb(PORT + 3, 0x03); // disable DLAB, set 8 bits per word, one stop bit, no parity
+ outb(PORT + 2, 0xC7); // enable and clear FIFOs, set to maximum threshold
+ // outb(port + 4, 0x0B); // TODO copied this from osdev wiki but i don't think you need it here
+ outb(PORT + 4, 0x1E); // set in loopback mode for test
+ outb(PORT + 0, 0xAE); // test by sending 0xAE
+
+ uint8_t response = inb(PORT + 0);
+ if (response != 0xAE) {
+ // TODO panic here?
+ return -1;
+ }
+
+ // disable loopback, enable IRQs
+ outb(PORT + 4, 0x0F);
+ return 0;
+}
+
+uint8_t serial_in(void) {
+ // wait for data to be available
+ while ((inb(PORT + 5) & 0x01) == 0);
+ return inb(PORT);
+}
+
+void serial_out(uint8_t ch) {
+ // wait for output to be free
+ while ((inb(PORT + 5) & 0x20) == 0);
+ outb(PORT, ch);
+}
+
+void serial_out_str(const char *str) {
+ for (; *str != '\0'; str++) {
+ serial_out(*str);
+ }
+}
diff --git a/src/arch/x86_common/include/bindings.h b/src/arch/x86_common/include/bindings.h
new file mode 100644
index 0000000..9406774
--- /dev/null
+++ b/src/arch/x86_common/include/bindings.h
@@ -0,0 +1,53 @@
+#pragma once
+
+#include <stdint.h>
+
+static inline uint8_t inb(uint16_t port) {
+ uint8_t ret;
+ __asm__ volatile ("inb %1, %0" : "=a"(ret) : "Nd"(port));
+ return ret;
+}
+
+static inline void outb(uint16_t port, uint8_t val) {
+ __asm__ volatile ("outb %0, %1" : : "a"(val), "Nd"(port));
+}
+
+static inline uint16_t inw(uint16_t port) {
+ uint16_t ret;
+ __asm__ volatile ("inw %1, %0" : "=a"(ret) : "Nd"(port));
+ return ret;
+}
+
+static inline void outw(uint16_t port, uint16_t val) {
+ __asm__ volatile ("outw %0, %1" : : "a"(val), "Nd"(port));
+}
+
+static inline uint32_t inl(uint16_t port) {
+ uint32_t ret;
+ __asm__ volatile ("inl %1, %0" : "=a"(ret) : "Nd"(port));
+ return ret;
+}
+
+static inline void outl(uint16_t port, uint32_t val) {
+ __asm__ volatile ("outl %0, %1" : : "a"(val), "Nd"(port));
+}
+
+static inline void io_wait(void) {
+ outb(0x80, 0);
+}
+
+static inline void sti(void) {
+ __asm__ volatile ("sti");
+}
+
+static inline void cli(void) {
+ __asm__ volatile ("cli");
+}
+
+static inline void int_wait(void) {
+ __asm__ volatile ("sti; hlt");
+}
+
+static inline void halt(void) {
+ __asm__ volatile ("cli; hlt");
+}
diff --git a/src/arch/x86_common/include/mboot.h b/src/arch/x86_common/include/mboot.h
new file mode 100644
index 0000000..d1ca1a0
--- /dev/null
+++ b/src/arch/x86_common/include/mboot.h
@@ -0,0 +1,11 @@
+#pragma once
+
+#include <shim.h>
+#include <memory.h>
+
+/**
+ * Loads the multi boot information
+ * @param mboot_info - the pointer passed from multiboot2
+ * @param shim_info - the info to be collected by shim
+ */
+void mboot_load_info(long mboot_magic, const volatile void *mboot_data_ptr, volatile struct boot_info *shim_info);
diff --git a/src/arch/x86_common/include/pic.h b/src/arch/x86_common/include/pic.h
new file mode 100644
index 0000000..2a4670e
--- /dev/null
+++ b/src/arch/x86_common/include/pic.h
@@ -0,0 +1,31 @@
+#pragma once
+
+#define PIC_REMAP_OFFSET 0x20
+
+/**
+ * Remaps the pie, i.e. initializes it
+ */
+void pic_remap(void);
+
+/**
+ * Masks an external irq to stop firing until un masked
+ * @param irq - the irq to mask
+ */
+void pic_mask(int irq);
+
+/**
+ * Unmasks an external irq to allow interrupts to continue for that irq
+ * @param irq - the irq to unmask
+ */
+void pic_unmask(int irq);
+
+/**
+ * Disabled the pick
+ */
+void pic_disable(void);
+
+/**
+ * Tells the pick that the interrupt has ended
+ * @param irq - the irq that has ended
+ */
+void pic_eoi(int irq);
diff --git a/src/arch/x86_common/mboot.c b/src/arch/x86_common/mboot.c
new file mode 100644
index 0000000..db82b9d
--- /dev/null
+++ b/src/arch/x86_common/mboot.c
@@ -0,0 +1,283 @@
+#include <shim.h>
+#include <lib.h>
+#include <stdint.h>
+#include <panic.h>
+#include <mboot.h>
+
+#define MBOOT_HEADER_MAGIC 0x36D76289
+
+#define MBOOT_CMDLINE 1
+#define MBOOT_MEMORY_MAP 6
+#define MBOOT_FRAMEBUFFER 8
+#define MBOOT_ELF_SYMBOLS 9
+#define MBOOT_OLD_RSDP 14
+#define MBOOT_NEW_RSDP 15
+
+struct mboot_info {
+ uint32_t total_size;
+ uint32_t reserved;
+ char tags[];
+};
+
+struct mboot_tag {
+ uint32_t type;
+ uint32_t size;
+ char data[];
+};
+
+struct mboot_tag_elf_sections {
+ uint32_t type;
+ uint32_t size;
+ uint16_t num;
+ uint16_t entsize;
+ uint16_t shndx;
+ uint16_t reserved;
+ char sections[];
+};
+
+struct mboot_tag_elf_sections_entry {
+ uint32_t sh_name;
+ uint32_t sh_type;
+ uint64_t sh_flags;
+ uint64_t sh_addr;
+ uint64_t sh_offset;
+ uint64_t sh_size;
+ uint32_t sh_link;
+ uint32_t sh_info;
+ uint64_t sh_addralign;
+ uint64_t sh_entsize;
+};
+
+struct mboot_mmap_entry {
+ uint64_t addr;
+ uint64_t len;
+ uint32_t type;
+ uint32_t zero;
+};
+
+struct mboot_tag_mmap {
+ uint32_t type;
+ uint32_t size;
+ uint32_t entry_size;
+ uint32_t entry_version;
+ struct mboot_mmap_entry entries[];
+};
+
+
+struct mboot_tag_old_rsdp {
+ uint32_t type;
+ uint32_t size;
+ char rsdp[];
+};
+
+struct mboot_tag_new_rsdp {
+ uint32_t type;
+ uint32_t size;
+ char rsdp[];
+};
+
+struct mboot_tag_cmdline {
+ uint32_t type;
+ uint32_t size;
+ uint8_t cmdline[];
+};
+
+struct mboot_tag_framebuffer {
+ uint32_t type;
+ uint32_t size;
+ uint64_t framebuffer_addr;
+ uint32_t framebuffer_pitch;
+ uint32_t framebuffer_width;
+ uint32_t framebuffer_height;
+ uint8_t framebuffer_bpp;
+ uint8_t framebuffer_type;
+ uint16_t reserved;
+};
+
+static void read_symbols(
+ volatile struct boot_info *shim_info,
+ volatile struct mboot_tag_elf_sections *sections
+) {
+ shim_info->symbol_table = (void * volatile) sections->sections;
+
+// struct mboot_elf_section_header *section =
+// (struct mboot_elf_section_header *) (layout->elf_section_headers);
+//
+// for (uint32_t i = 0; i < layout->num; i++) {
+// char buf[20];
+//
+// ultoa(i, buf, 10);
+// serial_out_str("[");
+// serial_out_str(buf);
+// serial_out_str("]\t");
+//
+// serial_out_str((char *)(kaddr(symtab) + section->sh_name));
+// serial_out('\t');
+//
+// ultoa(section->sh_type, buf, 16);
+// serial_out_str("type: 0x");
+// serial_out_str(buf);
+// serial_out('\t');
+//
+// ultoa(section->sh_addr, buf, 16);
+// serial_out_str("addr: 0x");
+// serial_out_str(buf);
+// serial_out('\t');
+//
+// ultoa(section->sh_offset, buf, 16);
+// serial_out_str("offset: 0x");
+// serial_out_str(buf);
+// serial_out('\n');
+//
+// section++;
+// }
+}
+
+static void read_cmdline(
+ volatile struct boot_info *shim_info,
+ volatile struct mboot_tag_cmdline *cmdline
+) {
+ uint32_t size = cmdline->size - 8;
+ if (size >= CMDLINE_MAX)
+ size = CMDLINE_MAX; // truncate :(
+ memcpyv(shim_info->cmdline, cmdline->cmdline, size);
+ shim_info->cmdline[size] = '\0';
+}
+
+static void read_framebuffer(
+ volatile struct boot_info *shim_info,
+ volatile struct mboot_tag_framebuffer *framebuffer
+) {
+ shim_info->fb.addr = framebuffer->framebuffer_addr;
+ shim_info->fb.width = framebuffer->framebuffer_width;
+ shim_info->fb.height = framebuffer->framebuffer_height;
+ shim_info->fb.pitch = framebuffer->framebuffer_pitch;
+ shim_info->fb.bit_depth = framebuffer->framebuffer_bpp;
+}
+
+static const char *segment_type[] = {
+ "Reserved",
+ "Free",
+ "Reserved",
+ "ACPI Reserved",
+ "Hibernation",
+ "Defective",
+ "Unknown"
+};
+
+static void read_memory_map(
+ volatile struct boot_info *shim_info,
+ volatile struct mboot_tag_mmap *map
+) {
+ int idx = 0;
+ uintptr_t i = (uintptr_t)map->entries;
+ kprintf("MEMORY MAP\n");
+ char buf[20];
+ for (;
+ i < (uintptr_t)map->entries + map->size;
+ i += map->entry_size, idx++
+ ) {
+ struct mboot_mmap_entry *seg = (struct mboot_mmap_entry *) i;
+ const char *type = NULL;
+ if (seg->type > 4)
+ type = segment_type[6];
+ else
+ type = segment_type[seg->type];
+ kprintf("ADDR: %16p LEN: %4s TYPE: %s (%d)\n",
+ (void *)seg->addr,
+ btoa(seg->len, buf),
+ type,
+ seg->type
+ );
+ if (seg->type != 1 || seg->len < 1)
+ continue;
+ shim_info->map.entries[idx].addr = seg->addr;
+ shim_info->map.entries[idx].len = seg->len;
+ }
+ shim_info->map.entry_count = idx;
+}
+
+static void read_old_rsdp(
+ volatile struct boot_info *shim_info,
+ volatile struct mboot_tag_old_rsdp *rsdp
+) {
+ if (shim_info->acpi_table != NULL)
+ return; // xsdp is newer and has been loaded
+ shim_info->acpi_table = (void *volatile) rsdp->rsdp;
+}
+
+static void read_new_rsdp(
+ volatile struct boot_info *shim_info,
+ volatile struct mboot_tag_new_rsdp *rsdp
+) {
+ shim_info->acpi_table = (void *volatile) rsdp->rsdp;
+}
+
+void mboot_load_info(
+ long mboot_magic,
+ volatile const void *mboot_data_ptr,
+ volatile struct boot_info *shim_info
+) {
+
+ if (mboot_magic != MBOOT_HEADER_MAGIC)
+ panic("invalid multiboot magic");
+
+ memsetv(shim_info, 0, sizeof(struct boot_info));
+
+ struct mboot_info *mboot_info = (struct mboot_info *) mboot_data_ptr;
+ const char *mboot_end = ((char *) mboot_info) + mboot_info->total_size;
+
+ char *tag_ptr = mboot_info->tags;
+
+ while (tag_ptr < mboot_end) {
+ struct mboot_tag *tag = (struct mboot_tag *) tag_ptr;
+
+ switch (tag->type) {
+ case MBOOT_CMDLINE:
+ read_cmdline(
+ shim_info,
+ (struct mboot_tag_cmdline *) tag
+ );
+ break;
+ case MBOOT_FRAMEBUFFER:
+ read_framebuffer(
+ shim_info,
+ (struct mboot_tag_framebuffer *) tag
+ );
+ break;
+ case MBOOT_MEMORY_MAP:
+ read_memory_map(
+ shim_info,
+ (struct mboot_tag_mmap *) tag
+ );
+ break;
+ case MBOOT_ELF_SYMBOLS:
+ read_symbols(
+ shim_info,
+ (struct mboot_tag_elf_sections *) tag
+ );
+ break;
+ case MBOOT_OLD_RSDP:
+ read_old_rsdp(
+ shim_info,
+ (struct mboot_tag_old_rsdp *) tag
+ );
+ break;
+ case MBOOT_NEW_RSDP:
+ read_new_rsdp(
+ shim_info,
+ (struct mboot_tag_new_rsdp *) tag
+ );
+ break;
+ default:
+ break;
+ }
+
+ int size = tag->size;
+ if (size % 8 != 0) {
+ size += 8 - (size % 8);
+ }
+
+ tag_ptr += size;
+ }
+}
generated by cgit v1.2.3-freya (git 2.51.0) at 2025-09-22 19:54:53 +0000