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-rw-r--r--.gitignore1
-rw-r--r--src/arch/amd64/shim.c74
2 files changed, 75 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore
index 378eac2..fb81a73 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1,2 @@
build
+compile_flags.txt
diff --git a/src/arch/amd64/shim.c b/src/arch/amd64/shim.c
index 28ba8a0..c72a59b 100644
--- a/src/arch/amd64/shim.c
+++ b/src/arch/amd64/shim.c
@@ -1,3 +1,77 @@
+#include <stdint.h>
+
+#define PG_PRESENT 0x0000'0000'0000'0001
+#define PG_READ_WRITE 0x0000'0000'0000'0002
+#define PG_USER_SUPERVISE 0x0000'0000'0000'0004
+#define PG_WRITE_THROUGH 0x0000'0000'0000'0008
+#define PG_CACHE_DISABLE 0x0000'0000'0000'0010
+#define PG_ACCESSED 0x0000'0000'0000'0020
+#define PG_EXECUTE_DISABLE 0x8000'0000'0000'0000
+
+// PAGE MAP LEVEL 4 ENTRY
+struct pml4 {
+ uint64_t present : 1;
+ uint64_t rw : 1;
+ uint64_t user_supervisor : 1;
+ uint64_t write_through : 1;
+ uint64_t cache_disable : 1;
+ uint64_t accessed : 1;
+ uint64_t _reserved : 6;
+ uint64_t address : 40;
+ uint64_t _reserved_2 : 11;
+ uint64_t execute_disable : 1;
+};
+
+// PAGE DIRECTORY POINTER TABLE ENTRY
+struct pdpte {
+ uint64_t present : 1;
+ uint64_t rw : 1;
+ uint64_t user_supervisor : 1;
+ uint64_t write_through : 1;
+ uint64_t cache_disable : 1;
+ uint64_t accessed : 1;
+ uint64_t _reserved : 1;
+ uint64_t page_size : 1;
+ uint64_t _reserved_2 : 2;
+ uint64_t address : 40;
+ uint64_t _reserved_3 : 11;
+ uint64_t execute_disable : 1;
+};
+
+// PAGE DIRECTORY ENTRY
+struct pde {
+ uint64_t present : 1;
+ uint64_t rw : 1;
+ uint64_t user_supervisor : 1;
+ uint64_t write_through : 1;
+ uint64_t cache_disable : 1;
+ uint64_t accessed : 1;
+ uint64_t _reserved : 1;
+ uint64_t page_size : 1;
+ uint64_t _reserved_2 : 2;
+ uint64_t address : 40;
+ uint64_t _reserved_3 : 11;
+ uint64_t execute_disable : 1;
+};
+
+// PAGE TABLE ENTRY
+struct pte {
+ uint64_t present : 1;
+ uint64_t rw : 1;
+ uint64_t user_supervisor : 1;
+ uint64_t write_through : 1;
+ uint64_t cache_disable : 1;
+ uint64_t accessed : 1;
+ uint64_t dirty : 1;
+ uint64_t mem_type : 1;
+ uint64_t global : 1;
+ uint64_t _reserved : 3;
+ uint64_t address : 40;
+ uint64_t _reserved_2 : 7;
+ uint64_t protection_key : 4;
+ uint64_t execute_disable : 1;
+};
+
// entry point for amd64
void amd64_shim(void *boot_info) {